Combating Dark Silicon with Power-Agile Systems and Many-Accelerator Architectures
Researchers have predicted that, over the next decade, increases in power density will make it necessary to leave sections of a microchip powered off. This threat to the computer industry, referred to as Dark Silicon, will end the performance gains that industry has seen from Moore's Law and limit the increasing benefits society has reaped from advances in computing. The computing industry needs new architecture paradigms, operating system support, and circuit designs in order to design and operate the computing systems of the future. All layers and players in the design space---the entire village---will need to work together to address this looming threat and propel computing to the future. This talk provides two examples from our work that illustrate new cross-layer approaches to energy management and microprocessor design.
The first example, OS-hardware energy management, demonstrates that traditional layers of abstractions---such as between hardware and operating system---need to be redesigned to agilely respond to changing energy and performance requirements. We introduce the concept of Inefficiency that can be used to express the energy required to execute an application and communicate system and user energy priorities. We are currently developing a new operating system and with hardware interfaces called Agile-Android to test some of these ideas. We present a set of algorithms that can tune CPU and memory frequency and voltage to stay under and Inefficiency budget.
The second example describes the challenge of integrating specialized hardware accelerators on-chip. While accelerators are touted as a potential solution to Dark Silicon, open questions- --like how to select the right accelerators for the highest coverage of the application and how to design memory systems for these data hungry accelerators---remain. We are developing a new set of tools to classify communication in workloads (Sigil and SynchroTrace) and also discover reconfigurable accelerators that can cover more of the workload than a single specialized accelerator.
Bio: Mark Hempstead an Associate Professor in the Department of Electrical and Computer Engineering at Tufts University. Prior to joining Tufts, he was the Junior Colehower Chair Assistant Professor at Drexel University. His research group, the Tufts Computer Architecture Lab (TCAL), investigates methods to increase energy efficiency across the boundaries of circuits, architecture, and systems. Currently, they are exploring the performance and energy benefits of heterogeneity in future microprocessor architectures and methodologies for communication-aware workload characterization. His group has published innovations in several different research communities including high performance computer architecture, embedded systems, workload characterization, mobile-systems, and wireless sensor networks.
Dr. Hempstead received a BS in Computer Engineering from Tufts University and his MS and PhD in Engineering from Harvard University working with Professors David Brooks and Gu- Yeon Wei. He received the NSF CAREER award in 2014 and the Drexel College of Engineering Excellence in Research Award in 2014. He was honored for his achievements in teaching with the 2014 Drexel University Allen Rothwarf Award for Teaching Excellence given to one junior faculty member a year. He was the winner of the industry sponsored SRC student design contest in 2006 and Best Paper Nominee in HPCA 2012. Before beginning a faculty position, Dr. Hempstead spent five months in the Cambridge, UK R&D group of ARM Ltd.