Taylor Expansion Diagrams: a New Representation for RTL Verification

October 3, 2001
1:30 pm - 2:30 pm
Halligan 111


We present a new, compact, canonical representation for arithmetic expressions, called Taylor Expansion Diagram. This representation is based on an novel non-binary decomposition principle. It treats the expression as a continuous, differentiable function over symbolic variables and applies Taylor series expansion recursively over its variables. The resulting Taylor Expansion Diagram (TED), is canonical for a fixed ordering of variables. We present a theory of TED, and show how to obtain the reduced, normalized representation. We demonstrate that it has linear space complexity for arbitrarily complex polynomials, while time complexity to generate the representation is comparable to that of *BMD and KBMD. The proposed TED representation is intended to facilitate the verification of RTL specifications and hardware implementations of arithmetic designs, and especially the equivalence checking of complex algebraic and arithmetic expressions that arise in symbolic verification.