Static Scheduling of Multiple Asynchronous Domains for Functional Verification
Communication scheduling is a technique used by many parallel verification systems to coordinate data transfer between multiple processing elements. This system-wide data transfer is generally synchronized to a high-speed system clock which pipelines data between processing elements in a point-to-point fashion. While it is generally straightforward to derive a fixed relationship between a system clock and numerous phase-related clocks of a design under test, mapping complications arise if a user design contains multiple clocks that operate asynchronously to each other. Specifically, multi- clock domain behavior presents significant scheduling challenges for parallel verification systems, such as logic emulators. In this talk, I describe scheduling and synthesis techniques that address the synchronization problem for designs with multiple asynchronous clock domain signals. Specific approaches for latch evaluation, memory evaluation, and inter-FPGA data transport are addressed. It is shown that when our heuristic approach is applied to an FPGA-based logic emulator, evaluation fidelity is maintained and increased design evaluation performance can be achieved for large benchmark designs with multiple asynchronous clock domains.