Handling Behavior Components in Multi-Level Fault Simulation
System level modeling and testing is an important part of engineering design. As systems grow in complexity, designers increasingly rely on component reuse and commercial-off-the-shelf (COTS) components. Frequently, these components are described at a high level of abstraction (behaviorally), which complicates system simulation and testing. This presentation discusses the trade-offs of using behavioral components in a design, specifically as it relates to fault simulation. We examine how to represent behavioral faults and their impact on timing accuracy. We also introduce our multi-level concurrent fault simulator (MCS) which can accept any combination of gate level and behavioral models in a single kernel architecture. Fault simulation results are presented for a multi-level design in order to demonstrate our simulator's capabilities and performance.