"FinFETs: Thermal Modeling, Analysis, and Circuit Design"

June 26, 2006
10:00 - 11:30 AM
Halligan 111-A
Speaker: Brian Swahn, Tufts University
Host: Soha Hassoun


As device dimensions shrink into the nanometer range, power and performance constraints prohibit the longevity of traditional MOS devices in circuit design. FinFETs, a quasi-planar double-gated device, promise to replace traditional planar MOSFETs in future technology generations. FinFETs are formed by creating a silicon fin which protrudes out of the wafer, wrapping a gate around the fin, and then doping the ends of the fin to form the source and drain regions. FinFETs curb planar MOSFET short channel effects by introducing multiple gates around the channel. The improved gate control reduces leakage current and delivers high drive current. FinFETs further improve over traditional MOSFETs by independently operating the two gates, allowing for dynamic control of the threshold voltage and for new circuit design techniques. The major contributions of this thesis are design and analysis techniques for finFETs. This thesis investigates several finFET challenges: a) understanding device-level thermal effects, b) creating a distributed single-fin thermal model, c) providing a multiple-fin thermal model, d) introducing an electro-thermal simulation methodology for finFETs, e) examining finFET sensitivity to process variations, f) creating a novel metric, METS, that captures device robustness to electro-thermal sensitivities, and g) comparing finFETs to state-of-the-art 32nm bulk technologies and examining circuit-level optimization techniques. Our work is novel because it provides the first study of multi-fin devices and because it investigates thermally-aware finFET-based circuit design. Our thermal sensitivity metric is the first to capture device robustness to self-heating. Our finFET and 32nm bulk MOSFET circuit-level comparisons provide insight into future technologies. Our work paves the way for future nanometer device and circuit-level design.