Hot Spots Inside Cool Chips: Coupling Measurements and Computations to Get Full 3D Temperature Fields of Complex Submicron Devices

Abstract

With ever increasing physical complexity, shrinking feature sizes, and higher local power densities, heat extraction has become a serious impediment in the continuing evolution of electronic devices. In short, as devices have shrunk, their cooling problems have grown, to the point that many now wonder whether Moore’s law has finally crashed against the laws of thermodynamics! Since we’re not about to curb our appetite for electronic processing, we need to seek effective solutions to the unavoidable thermal issues, and to do so, we simply need to first improve our knowledge of the actual temperature distributions within the devices. Indeed, the direct knowledge of thermal behavior is a necessary condition in efforts to improve analysis and design, shorten design cycle time, assess reliability, and diagnose defects. Ironically though, the same culprits that have accentuated the thermal issues – device complexity and shrinking feature sizes – make temperature measurements a challenging pursuit. Put simply: now that we agree that we cannot afford not to know internal temperatures, and know them well, how can we measure what we cannot see or access? This talk will address the issues of temperature determination by novel measurement techniques, both direct and computationally-enhanced.

We will examine the applicability and efficacy of a newly developed thermoreflectance thermometry experimental system capable of scanning non-invasively and non-destructively the transient surface temperature of pulsed microelectronic devices with submicron spatial and sub-microsecond temporal resolutions. We will then explore a powerful new approach that provides full three-dimensional thermal characterization of complex three-dimensional devices by coupling two-dimensional surface temperature measurements with an ultra-fast self-adaptive three-dimensional computational engine. By bringing together measurement and computation, it becomes possible for the first time to non-invasively extract the transient three-dimensional thermal behavior of nanoscale embedded features that cannot otherwise be accessed. The methods will be demonstrated on standard and specially fabricated CMOS test devices.