Defect Tolerance of Molecular Crossbar Architectures
Improvements in lithography-based chip manufacturing technology have propelled an astonishing growth of electronic systems. However, serious challenges to this trend are due to fundamentalphysical limits of CMOS technology. Emerging nanotechnologies such as carbon nanotubes promise to supercede CMOS technology in future.
Self-assembled nano-fabrication processes yield regular and reconfigurable devices. However, defect densities in this emerging nanotechnology are higher than those in conventional lithography- based VLSI. In this talk, defect tolerant techniques for crossbar nano-architectures will be discussed. We present an application-independent defect-tolerant design flow to minimize customized post-fabrication design efforts to be performed per chip. In this flow, higher level design steps are not needed to be aware of the existence and the location of defects in the chip. Only a final mapping step is required to be defect-aware. Application independence of this flow minimizes the amount of per chip design steps, making it appropriate for high volume production. We also analyze the manufacturing yield of molecular crossbars under different defect distribution models.