Optimal Pipelined Route Construction

September 10, 2003
2:50pm - 4:00pm
Halligan 111


Shrinking process geometries and the challenges in clocking methodologies give rise to new problems in routing and buffer insertion. A particular need is the construction of multi-cycle, latency-optimal, on-chip routes. This talk will explore simultaneous routing and buffer insertion in the context of single and multiple clock domains (i.e. Globally Asynchronous Locally Synchronous Architectures). We demonstrate the pressing need for this type of routing for several technologies. We examine optimal route construction using registers and buffers. We also describe how to optimally perform routing using level-sensitive latches. To alleviate clock routing problems and further optimize the route, we examine the constraints needed to implement wave-pipelined routes. We finally describe optimal routing in Globally Asynchronous, Locally Synchronous Architectures. This is joint work with Chuck Alpert at IBM Austin Research labs, and Arvind Vidyarthi at Tufts.