PhD Research Talk: Through Silicon Via Analysis for the Design of 3-D Integrated Circuits

April 4, 2011
Halligan 111B


Stacking multiple dies to form 3-D ICs has emerged as a promising technology to reduce interconnect delay and power, to increase device density, and to achieve heterogeneous integration. Through- silicon vias (TSVs) are metallic wires that connect different dies, and are a key enabling technology for 3-D ICs. TSVs can be used for routing signals, for power delivery, and for heat extraction. TSV- manufacturing advances are well underway. However, there is little experience in designing optimally with TSVs.

I will talk about challenges and best design strategies for TSVs. Signal TSVs induce noise in the substrate and affect neighboring devices. I will discuss a novel technique, GND Plug, to mitigate TSV- induced noise. I will describe a comparative study to investigate the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. TSVs occupy silicon real-estate and impact the device density. I will provide four algorithms, in an iterative framework, to minimize the number of TSVs needed for power delivery network. Unlike prior work, these algorithms can be applied early in the design stages when only functional block-level behaviors and a floorplan are available. Finally, I will talk about using Carbon Nanotubes to design the TSVs and power grid. Overall, the talk advances the state-of-art in 3-D design.