Off-Chip Bandwidth: The New Wall in The Multicore Era
With the number of on-chip cores consistently increasing, we would expect a corresponding increase in performance. However, there are several "walls" in the face of this ultimate goal. For single core architecture, we had the memory wall, which still exists in multicore era. Then the power wall was one of the main reasons we shifted from single core to multicore processors.
In this talk, I will discuss the new wall in the multicore/manycore era: the off-chip bandwidth requirement. The cores need to be fed with data and instructions, and need to spill data back to the memory or off-chip caches. This puts a lot of pressure on buses, memory ports, and the not-very-scalable pads and pins. I will discuss several techniques that we developed to decrease off-chip bandwidth requirement with little hardware cost and minimal, if at all, impact on overall performance. I will end my talk with a short discussion of my other projects and the new project I am about to start.
Bio: Mohamed Zahran received his Ph.D. in Electrical and Computer Engineering from University of Maryland at College Park. He worked as a research scientist at The George Washington University for a year, before joining the Electrical Engineering department at City College of City University of New York. In 2010 he moved to NYU as a research associate professor. His research interest spans several aspects of computer architecture, such as microarchitecture, memory system design for manycore architectures, hardware support for secure platforms, and hardware/software interaction. Recently he started exploring biologically inspired computing especially its application to microprocessor design. Zahran is a senior member of IEEE, senior member of ACM, and Sigma Xi scientific honor society.