The Execution Migration Machine: Hardware-Level Thread Migration in a 110-Core Shared-Memory Multiprocessor
Chip multiprocessors with hundreds of cores are becoming a reality as technology nodes continue shrinking: it is now possible to combine hundreds of processor cores in a single chip. Building such massive- scale processors, however, brings new challenges. All those cores must be fed data to stay busy, and have to communicate with other cores over dramatically larger distances. These challenges, we believe, call for bold architectural innovations.
In this talk, we describe one such innovation: hardware-level thread migration. An enabling technology that accelerates intercore thread movement by several orders of magnitude, hardware-level migration has allowed us to design a novel shared memory scheme that can perform comparably to traditional directory-based coherence. Our proof-of- concept implementation of this technique in a 110-core shared-memory processor ASIC is the largest multicore to date in terms of core count.