Quick links:
Contact
Teaching
Publications
Background
Joel's college-of-engineering web page
Joel Grodstein - Publications
My CV
A quick list of publications:
- Closing the loop on morphogenesis: a mathematical model of morphogenesis by closed-loop reaction-diffusion, J.Grodstein, P.McMillen and M.Levin, Frontiers in Cell and Developmental Biology, Vol 11, Aug 2023
- A Computational Approach to Explaining Bioelectrically-induced Persistent, Stochastic Changes of Axial Polarity in Planarian Regeneration, J.Grodstein and M.Levin, Bioelectricity, Vol 4 #1, 2022
- Stability and Robustness Properties of Bioelectric Networks: A Computational Approach, J.Grodstein and M.Levin, Biophysics Rev. 2, Sept 2021
- A Fast Boolean Solver for choosing load/store addresses to test a CPU uncore, J. Grodstein et. al., North Atlantic Test Workshop 2011
- Test Vector Generation for Post-Silicon Delay Testing using SAT-Based Decision Problems, D. Tadesse, R.I. Bahar, J. Grodstein, Journal of Electric Testing, April 2011.
- AutoRex: An automated post-silicon clock tuning tool, D. Tadesse, J. Grodstein, R.I. Bahar, 2009 International Test Conference
- Fast Measurement of the "Non-deterministic Zone" in Microprocessor Debug using Maximum Likelihood Estimation, D. Tadesse, R. I. Bahar, J. Grodstein, VLSI Test Symposium 2008
- Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models, D. Tadesse, D. Sheffield, E. Lenge, R. I. Bahar, J. Grodstein, DATE 07
- Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations, R.Iris Bahar, Hui-Yuan Song, Kundan Nepal, Joel Grodstein. IEEE T.CAD. Dec 2006.
- Accurate Timing Analysis using SAT and Pattern-Dependent Delay Models, Desta Tadesse, Michael Black, Iris Bahar, Joel Grodstein.. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2006.
- Symbolic Failure Analysis of Complex CMOS Circuits Due to Excessive Leakage Current and Charge Sharing, R.Iris Bahar, Hui-Yuan Song, Kundan Nepal,Joel Grodstein, IEEE T.CAD., V.24#4, Apr 2005
- RESTA: A Robust, Extendable Symbolic Timing Analysis Tool, K.Nepal, H.Y.Song, R.I.Bahar, J.Grodstein, GLSVLSI 2004 Poster.
- Automatic Generation of Critical-Path Tests for a Partial-Scan Microprocessor, J.Grodstein,D.Bhavsar,V.Bettada,R.Davies, ICCD ’03.
- Symbolic Failure Analysis of Custom Circuits Due to Excessive Leakage Current, H.Y.Song,S.Bohidar,R.I.Bahar,J.Grodstein, ICCD’03.
- Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations, H.Y.Song,R.I.Bahar,J.Grodstein, IWLS’02.
- Power and CAD Considerations for the 1.75 Mbyte, 1.2GHz L2 cache of the Alpha 21364 Microprocessor, J.Grodstein et.al., Great Lakes Symp. on VLSI, April ’02.
- An ADD-Based Symbolic Analysis of Leakage Current in CMOS Circuits, H.Y.Song,R.I.Bahar,J.Grodstein, IWLS’01 poster.
- A 1.2GHz Alpha Microprocessor with 44.8GB/s Chip Pin Bandwidth, A.Jain, J.Grodstein, et.al.,ISSCC ’01.
- Static Race Verification for Networks with Reconvergent Clocks, J. Grodstein et.al., ICCD ’98
- A Low-Cost 300 Mhz RISC CPU with Attached Media Processor, S.Santhanam, J.Grodstein,et.al.,ISSCC ’98 & in IEEE J. Solid State Circuits, Vol 33, #11, Nov. ‘98
- Logic Decomposition During Technology Mapping, E.Lehman,Y.Watanabe,J.Grodstein,et.al., IEEE Trans. CAD, Aug 1997
- A Delay Model for Logic Synthesis of Continuously-Sized Networks, J. Grodstein et. al., ICCAD '95
- Logic Decomposition During Technology Mapping, E. Lehman, Y. Watanabe, J. Grodstein, et. al.,ICCAD '95
- Optimal Latch Mapping and Retiming Within a Tree, J. Grodstein et. al., ICCAD '94.
- A Simple Algorithm for Fanout Optimization using High-Performance Buffer Libraries, Kodandapani, Grodstein, et. al., ICCAD '93
- Automatic Detection of MOS Synchronizers for Timing Verification, J. Grodstein et. al., ICCAD '91
- Timing Verification on a 1.2M-Device Full-Custom CMOS Design, J.Pan, J.Grodstein et al, DAC 1991
- Race Detection for Two-Phase Systems, J. Grodstein et. al., ICCAD '90
- Constraint Identification for Timing Verification, J. Grodstein et. al., ICCAD '90
- System, Process, and Design Implications of a reduced-supply-voltage microprocessor, R.Allmon, J.Grodstein, et.al., ISSCC ’90.
- Spice-Decsim Interface, J. Grodstein et. al., Colorado Microelectronics Conference, 1989.
- Sisyphus: An Environment for Simulation, J. Grodstein et. al., ICCAD '87
Quick links:
Contact
Teaching
Publications
Background
Joel's college-of-engineering web page