Welcome to EE126 and EE194SIM! The goals of this course are to present concepts of embedded System Design, while considering design for testability issues.

This course will provide students with a thorough understanding of computer design including pipelining, memory concepts and interfacing with peripherals. The real world aspects of the design process including design for testability for manufacturing will be discussed.Current articles from journals will also be assigned so students will get the opportunity to interpret state of the art developments in the field.  Students will use VHDL and Verilog to model computer designs, download them to FPGA's and modify them for performance and testability analysis.The project will use the Xilinx tool suite and other industrial testbench products.  The course has a mandatory laboratory component and an option for a final lab that can be counted as a senior project (EE97). Students design a "Virtual Student" using the Xilinx CAD tool suite. 
 
Meeting Time: Monday- Wednesday 5:00-6:20pm

Textbooks: 
 

•       "HDL Chip Design" by Douglas Smith, Doone Publications, AL.
  
  
•       "Rapid Prototyping of Digital Systems", by J. O. Hamblen and M. Furman, Kluwer      Academic Publishers.

• "Computer Architecture, A Quantitative Approach" by Patterson and Hennessey, Morgan Kauffman Publishers.
  
  
• "Computer Organization and Design, By D. Patterson and J. Hennessy. Morgan Kaufmann Publishers.
  
  
• "Design for Test, for digital ICs and Embedded CORE Systems", by Alfred Couch, Prentice Hall publishers.

Lab Teaching Assistants:

TA: Naomi Lee 
Office: Room 133, Halligan Hall 

Office Hours:TBD

• The Real World: Reliable Designs, Design process and test. (yield)
• Fault Simulation 
• Overview of computer architecture, instruction decode and examples of hardware that do it.
• Measuring System Performance 
• Introduction to hardware description languages, VHDL and Verilog
• Chip Architectures ASIC, FPGA and CPLDs and packaging. 
• Advanced Computer Architecture Concepts .
• Memory and I/O
• Embedded Core-Based Chip Design.
• Reuse Cores
• Built in Design for Testability
• Scan Testing 

Homework: Homework will consist of VHDL programming exercises as well as some book/essay type questions.

Quizzes: There will be announced quizzes. 

Laboratories: There are 5 mandatory laboratories and a 6^th is available for those wishing to do an EE97 project (seniors only). 

 Lab: There will be five labs consisting of design, hardwired implementation and simulation. If a pre-lab is required for a lab, then the Pre-lab will count as a homework assignment. Each student will submit an individual lab report. More information on lab requirements will be passed out next week. YOU MUST PASS THE LAB COMPONENT OF THE COURSE OR YOU WILL FAIL THE COURSE.

All VHDL program code and lab reports are to be the product of a single individual and not a collaboration. 

Course Grading: