Please read the Lab & Homework Procedures for EE202
| Homework | Reading | Problems | Due Date |
|---|---|---|---|
| Assgn #1:posted 1/13/98 | Chapter 1 and 2 | Chapter 2 problems 1,2,3,4(modified). For problem 4 write the RTL models as (1) Register level using R1 <- M[1] type of instructions. (2) Using the more abstract approach as described on page 22. Final problem: I made this one up. Do the rtl for the assembler program on the bottom of page 19. Do it at the register level. | Thursday 1/29/98 |
| Assgn #2:posted 2/26/98 | Chapter 3 | Chapter 3 problems 1,2,3,6,9. | Thursday 3/5/98 |
| Lab | Title | Due Date |
|---|---|---|
| Lab 1 | VHDL BASICS with Altera | 2/5/98 |