EE26 Advanced Digital Logic Systems

 

Spring Semester 2003

www.eecs.tufts.edu/~karen

 

In this course, we will investigate all phases of designing and implementing reliable digital systems.  We will learn how to implement our designs using PLD (Programmable Logic Devices). The course includes a laboratory devoted to design, implementation and  verification of digital logic systems. We will utilize the Xilinx and Altera software and FPGA/PLD hardware.

 

Textbooks: Contemporary Logic Design, by Randy Katz,  Prentice Hall  

 

References: " Digital Systems Design with Programmable Logic", Martin Bolton,                     Addison Wesley, Reading, MA

 

            Digital Logic and Computer Design, by Morris Mano, Prentice Hall,                  Englewood Cliffs, NJ

            Microprocessors and Programmed Logic" Second Edition by Kenneth L.                      Short, Prentice Hall, Englewood Cliffs, NJ

 

Class meeting time: Tuesday, Thursday, 5:25-:6:40pm, room Halligan 111

It is expected that if you need to miss a class that you will email the professor before the class time.

Instructor: Professor Karen Panetta

           

                  Office: Room  236 Halligan Hall

 

                  Email: karen@eecs.tufts.edu 

 

                  Office Hours:   Tuesday       6:50: 8:30

                                            Wednesday: 6:00: 7:30

 

Lab Teaching Assistant: Weyant Stone - wstone@eecs.tufts.edu (Office Hours: Tues. 1:30-3:30)

   Office: Room  137 (Conference Room) Halligan Hall

 

Homework Grader:  Weyant Stone

 

Tentative Topics:

 

1. Introduction: Phases of System Design and modeling.

 

2. Review of combinatorial circuits and sequential circuits.

 

3. Finite State Machines, 1 hot state design and asynchronous circuit design.

 

4. Introduction to PLD's and FPGAs,  and how to use them.

 

5. CMOS and diode implementation of PLDs

 

6. HDLs such as VHDL and Verilog

 

7. The Memory Unit, RTL, micro-operations

 

8. Design of the Arithmetic Circuit

 

9. Control logic Design 

 

10.  Microprocessor Design

11.   Testing and verification

 

Quiz: There will be a quiz given every Thursday, if time allows. The best 5 quizzes will be counted.  No make-up quizzes will be given.

 

Homework: There will be a homework assignment due every Thursday. Homework will be posted on the web page and available in the EE office. Solutions to the homework will be placed in a book in the EE office a week after the due date. Any assignments or laboratory reports not handed in during class time, MUST be date stamped and turned in at the front office.  All handouts given out in class will also be available in the EE office.

No late homework will be accepted.

 

Lab: There will be five labs consisting of design, hardwired implementation and

simulation. Any Pre-labs will count as a homework assignment. Each student will submit an individual lab report. All Lab reports will follow the posted lab write-up requirements posted on the ee26 web page. More information on lab requirements will be passed out next week.

 

Examinations: There will be a midterm and a final exam. The midterm exam will be given in class on:  Tuesday March 11, 2003. The final exam will be announced according to the university schedule. If you have a schedule conflict at any of the exam times for some unexpected reason, please get in touch with me or the EE secretary as soon as possible.

 

Course Grading:

 

Homework Average:    10%

Quizzes                        15%

Lab and oral

presentation                  20%

 

Midterm -exam             25%

 

Final Exam       30%