ES4 Introduction to Digital Logic Circuits

Class webpage: www.ece.tufts.edu/~karen/Classes/ES4

 

Descriptions and Goals:

This course will introduce students into the wonderful world of digital design. All aspects of design and implementation methods will be discussed. To enforce the theoretical concepts, we will use VHDL to model and simulate designs. Topics we will cover include number systems, codes and conversions. Two's complement representation. Boolean algebra and Karnaugh map minimization of Boolean expressions. We will then investigate logic gates and implement useful designs in the laboratory using SSI, MSI and LSI logic components. After covering combinational logic, we will introduce flip-flops and their characteristics. The course includes a MANDATORY laboratory devoted to design, implementation.

Prerequisites: ES3 Circuit Theory

 

Textbooks: Logic and Computer Design Fundamentals, by M.  Morris Mano and  Charles Kime, Prentice Hall,             Englewood Cliffs, NJ. Make sure it’s packaged with Xilinx software. Fourth Edition.

References:  Fundamentals of Digital Logic with VHDL Design,by Stephan Brown and Zvonko Vranesic. The publisher is McGraw Hill. ,Introduction to Digital Logic Design", John Hayes, Addison Wesley,  Reading, MA

 

Coordinator: Professor Karen Panetta

                  Office: Room  236 Halligan Hall

                  Email: karen@eecs.tufts.edu 

                  Office Hours: Monday:  3:00-5:00pm

                                         Thursday: 3:00-5:00pm

 

Teaching Assistant: Mr. James Pringle

Office: Room 137 Halligan Hall

Office Hours: Tuesday:           3:30-4:30pm

                        Thursday:         3:30-4:30pm

 

Specific Topics:

 

1.      Introduction to industrial system design of computers.

2.      Binary Systems, bits, base transformations (2 classes).

3.      AND, OR, NOT functions, truth tables, gates. (2)

4.       Alphanumeric codes, radix arithmetic. 

5.      2's complement representation. (2)

6.       Booelan theorems, algebraic simplification. (2)

7.       Functions, complements, duals, canonical forms.(2)

8.      Minterms, maxterms, Sum of Products,  Product of Sums ,  (2)

9.      NAND,NOR,XOR,XNOR gates, parity, gates with more than 2 inputs. (2)

10.  Karnaugh Maps (3)

11.  . NAND, NOR implementations, bubble manipulations. (2)

12.  Don't cares on K-maps, prime and essential prime implicants (2)

13.  MSI combinatorial functions, multiplexor  and decoders. (2)

14.  Introduction to sequential circuits. (1)

15.  SR, D, JK flip-flops, edge-triggered. (2)

16.  Counter design using flip-flops.(1)

17.  Moore and Mealy machines (3)

 

Assessment of  accomplishments

  • Mastering the material in this course is measured by:
  • Quizzes
  • Homework
  • Laboratory sessions
  • A midterm and final examination.

Each of these assessments is discussed in the following sections.

 

Quiz: There will be a quiz given every Wednesday.  Two of the lowest quiz grades will be dropped. No make-up quizzes will be given.

 

Homework: There will be a homework assignment due every Monday in class. Homeworks are posted on the web and the front office. It is your responsibility to retrieve the homework.  Solutions to the homework will be placed in a book in the ECE office the day after the due date. All handouts given in class are also available in the ECE office.

 

No late homework will be accepted.  If you cannot make class, turn in your homework in the front office and have it date stamped and put in your Teaching Assistant’s mailbox.

 

Collaboration is allowed and encouraged on homework. However, all students involved in collaboration must include the name of all collaborators at the top of their homework assignments. Failure to do so, will be considered plagiarism and will receive no credit.

 

Lab: There will be five labs consisting of design, hardwired implementation and simulation. If a pre-lab is required for a lab, then the Pre-lab will count as a homework assignment. Each student will conduct and individual lab and submit an individual lab report. More information on lab requirements will be passed out next week. YOU MUST PASS THE LAB COMPONENT OF THE COURSE with a 70% or better OR YOU WILL FAIL THE COURSE.

All VHDL program code and lab reports are to be the product of a single individual and not a collaboration.

 

Students will sign up for a specific lab session. If you cannot make your scheduled lab session, you must inform the laboratory assistant to make-up a lab.

Please refer to the detailed laboratory guidelines for ES4.

The labs may also have an exit quiz that will count toward each lab report grade.

 

Examinations: There will be one hour-exam and one final exam. The hour-exam will be given in class on:  Wednesday, March 12, 2008. The final exam will be announced according to the university schedule. If you have a schedule conflict for the hourly exam time for some unexpected reason, please get in touch with me or the ECE secretary as soon as possible.

 

Final Exam Date: Monday May 5th, 12PM

 

In Class attendance/presentation/professionalism:

5 additional bonus points will be added to the final exams of students who are present when randomly called upon anytime during the semester. If a student cannot make a class, professional courtesy requires a message to the instructor from a student indicating that they will not be present.  Incomplete grades will not be given for failure to fulfill class requirements. 

 

Course Grading:

Homework Average:    15%

Quizzes                        15%

Lab                              15% (must pass with a 70% or better)

First hour-exam            23%

Final Exam                   32%