/* Generated by the New Jersey Machine-Code Toolkit, version 0.5 */ /* command line: tools -no-reloc -data -indirect sparc:sparc -encoder sparc-enc /home/nr/toolkit/www/specs/sparc.spec */ #include #include "sparc-enc.h" #define sign_extend(N,SIZE) \ (((int)((N) << (sizeof(unsigned)*8-(SIZE)))) >> (sizeof(unsigned)*8-(SIZE))) /************** imode simm13! is (?noname?) i == 1 & simm13 = simm13 ***********/ static reg_or_imm_Instance imode(int simm13) { reg_or_imm_Instance _i = { imode_TAG }; if (!((unsigned)(simm13 + 4096) < 0x2000)) (*fail) ("simm13 = %d won't fit in 13 signed bits"); _i.u.imode.simm13 = simm13; return _i; } /************** rmode rs2 is (?noname?) i == 0 & rs2 = rs2 ***********/ static reg_or_imm_Instance rmode(unsigned /* [0..31] */ rs2) { reg_or_imm_Instance _i = { rmode_TAG }; _i.u.rmode.rs2 = rs2; return _i; } /************** generalA rs1 + reg_or_imm is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): i == 1 & rs1 = rs1 & simm13 = reg_or_imm.imode.simm13 | rmode => (?noname?) (?reg_or_imm:): i == 0 & rs1 = rs1 & rs2 = reg_or_imm.rmode.rs2 END (* reg_or_imm *) ***********/ static address__Instance generalA(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { address__Instance _i = { generalA_TAG }; _i.u.generalA.rs1 = rs1; _i.u.generalA.reg_or_imm = reg_or_imm; return _i; } /************** dispA rs1 + simm13! is (generalA) i == 1 & rs1 = rs1 & simm13 = simm13 ***********/ static address__Instance dispA(unsigned /* [0..31] */ rs1, int simm13) { address__Instance _i = { dispA_TAG }; if (!((unsigned)(simm13 + 4096) < 0x2000)) (*fail) ("simm13 = %d won't fit in 13 signed bits"); _i.u.dispA.rs1 = rs1; _i.u.dispA.simm13 = simm13; return _i; } /************** absoluteA simm13! is (generalA) i == 1 & rs1 = 0 & simm13 = simm13 ***********/ static address__Instance absoluteA(int simm13) { address__Instance _i = { absoluteA_TAG }; if (!((unsigned)(simm13 + 4096) < 0x2000)) (*fail) ("simm13 = %d won't fit in 13 signed bits"); _i.u.absoluteA.simm13 = simm13; return _i; } /************** indexA rs1 + rs2 is (generalA) i == 0 & rs1 = rs1 & rs2 = rs2 ***********/ static address__Instance indexA(unsigned /* [0..31] */ rs1, unsigned /* [0..31] */ rs2) { address__Instance _i = { indexA_TAG }; _i.u.indexA.rs1 = rs1; _i.u.indexA.rs2 = rs2; return _i; } /************** indirectA rs1 is (generalA) i == 0 & rs1 = rs1 & rs2 = 0 ***********/ static address__Instance indirectA(unsigned /* [0..31] */ rs1) { address__Instance _i = { indirectA_TAG }; _i.u.indirectA.rs1 = rs1; return _i; } /************** LDSB [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 9 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 9 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 9 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 9 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 9 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 9 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDSB(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSB_TAG }; _i.u.LDSB.address_ = address_; _i.u.LDSB.rd = rd; return _i; } /************** LDSH [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 10 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 10 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 10 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 10 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 10 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 10 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDSH(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSH_TAG }; _i.u.LDSH.address_ = address_; _i.u.LDSH.rd = rd; return _i; } /************** LDUB [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 1 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 1 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 1 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 1 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 1 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 1 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDUB(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDUB_TAG }; _i.u.LDUB.address_ = address_; _i.u.LDUB.rd = rd; return _i; } /************** LDUH [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 2 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 2 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 2 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 2 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 2 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 2 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDUH(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDUH_TAG }; _i.u.LDUH.address_ = address_; _i.u.LDUH.rd = rd; return _i; } /************** LD [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 0 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 0 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 0 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 0 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 0 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 0 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LD(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LD_TAG }; _i.u.LD.address_ = address_; _i.u.LD.rd = rd; return _i; } /************** LDSTUB [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 13 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 13 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 13 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 13 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 13 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 13 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDSTUB(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSTUB_TAG }; _i.u.LDSTUB.address_ = address_; _i.u.LDSTUB.rd = rd; return _i; } /************** SWAP_ [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 15 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 15 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 15 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 15 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 15 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 15 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance SWAP_(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SWAP__TAG }; _i.u.SWAP_.address_ = address_; _i.u.SWAP_.rd = rd; return _i; } /************** LDD [address_], rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 3 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 3 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 3 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 3 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 3 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 3 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance LDD(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDD_TAG }; _i.u.LDD.address_ = address_; _i.u.LDD.rd = rd; return _i; } /************** LDF [address_], fd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 32 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & fd = fd | dispA => (?noname?) (?address_:): op == 3 & op3 == 32 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & fd = fd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 32 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & fd = fd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 32 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & fd = fd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 32 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & fd = fd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 32 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & fd = fd END (* address_ *) ***********/ static instruction_Instance LDF(address__Instance address_, unsigned /* [0..31] */ fd) { instruction_Instance _i = { LDF_TAG }; _i.u.LDF.address_ = address_; _i.u.LDF.fd = fd; return _i; } /************** LDDF [address_], fd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 35 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & fd = fd | dispA => (?noname?) (?address_:): op == 3 & op3 == 35 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & fd = fd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 35 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & fd = fd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 35 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & fd = fd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 35 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & fd = fd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 35 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & fd = fd END (* address_ *) ***********/ static instruction_Instance LDDF(address__Instance address_, unsigned /* [0..31] */ fd) { instruction_Instance _i = { LDDF_TAG }; _i.u.LDDF.address_ = address_; _i.u.LDDF.fd = fd; return _i; } /************** LDC [address_], cd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 48 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & cd = cd | dispA => (?noname?) (?address_:): op == 3 & op3 == 48 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & cd = cd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 48 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & cd = cd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 48 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & cd = cd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 48 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & cd = cd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 48 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & cd = cd END (* address_ *) ***********/ static instruction_Instance LDC(address__Instance address_, unsigned /* [0..31] */ cd) { instruction_Instance _i = { LDC_TAG }; _i.u.LDC.address_ = address_; _i.u.LDC.cd = cd; return _i; } /************** LDDC [address_], cd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 51 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & cd = cd | dispA => (?noname?) (?address_:): op == 3 & op3 == 51 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & cd = cd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 51 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & cd = cd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 51 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & cd = cd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 51 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & cd = cd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 51 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & cd = cd END (* address_ *) ***********/ static instruction_Instance LDDC(address__Instance address_, unsigned /* [0..31] */ cd) { instruction_Instance _i = { LDDC_TAG }; _i.u.LDDC.address_ = address_; _i.u.LDDC.cd = cd; return _i; } /************** STB rd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 5 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 5 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 5 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 5 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 5 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 5 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance STB(unsigned /* [0..31] */ rd, address__Instance address_) { instruction_Instance _i = { STB_TAG }; _i.u.STB.rd = rd; _i.u.STB.address_ = address_; return _i; } /************** STH rd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 6 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 6 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 6 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 6 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 6 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 6 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance STH(unsigned /* [0..31] */ rd, address__Instance address_) { instruction_Instance _i = { STH_TAG }; _i.u.STH.rd = rd; _i.u.STH.address_ = address_; return _i; } /************** ST rd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 4 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 4 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 4 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 4 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 4 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 4 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance ST(unsigned /* [0..31] */ rd, address__Instance address_) { instruction_Instance _i = { ST_TAG }; _i.u.ST.rd = rd; _i.u.ST.address_ = address_; return _i; } /************** STD rd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 7 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 3 & op3 == 7 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 7 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 7 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 7 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 7 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance STD(unsigned /* [0..31] */ rd, address__Instance address_) { instruction_Instance _i = { STD_TAG }; _i.u.STD.rd = rd; _i.u.STD.address_ = address_; return _i; } /************** STF fd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 36 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & fd = fd | dispA => (?noname?) (?address_:): op == 3 & op3 == 36 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & fd = fd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 36 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & fd = fd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 36 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & fd = fd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 36 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & fd = fd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 36 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & fd = fd END (* address_ *) ***********/ static instruction_Instance STF(unsigned /* [0..31] */ fd, address__Instance address_) { instruction_Instance _i = { STF_TAG }; _i.u.STF.fd = fd; _i.u.STF.address_ = address_; return _i; } /************** STDF fd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 39 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & fd = fd | dispA => (?noname?) (?address_:): op == 3 & op3 == 39 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & fd = fd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 39 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & fd = fd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 39 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & fd = fd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 39 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & fd = fd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 39 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & fd = fd END (* address_ *) ***********/ static instruction_Instance STDF(unsigned /* [0..31] */ fd, address__Instance address_) { instruction_Instance _i = { STDF_TAG }; _i.u.STDF.fd = fd; _i.u.STDF.address_ = address_; return _i; } /************** STC cd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 52 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & cd = cd | dispA => (?noname?) (?address_:): op == 3 & op3 == 52 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & cd = cd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 52 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & cd = cd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 52 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & cd = cd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 52 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & cd = cd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 52 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & cd = cd END (* address_ *) ***********/ static instruction_Instance STC(unsigned /* [0..31] */ cd, address__Instance address_) { instruction_Instance _i = { STC_TAG }; _i.u.STC.cd = cd; _i.u.STC.address_ = address_; return _i; } /************** STDC cd, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 55 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & cd = cd | dispA => (?noname?) (?address_:): op == 3 & op3 == 55 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & cd = cd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 55 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & cd = cd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 55 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & cd = cd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 55 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & cd = cd | indirectA => (?noname?) (?address_:): op == 3 & op3 == 55 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & cd = cd END (* address_ *) ***********/ static instruction_Instance STDC(unsigned /* [0..31] */ cd, address__Instance address_) { instruction_Instance _i = { STDC_TAG }; _i.u.STDC.cd = cd; _i.u.STDC.address_ = address_; return _i; } /************** indexR rs1 + rs2 is (?noname?) i == 0 & rs1 = rs1 & rs2 = rs2 ***********/ static regaddr_Instance indexR(unsigned /* [0..31] */ rs1, unsigned /* [0..31] */ rs2) { regaddr_Instance _i = { indexR_TAG }; _i.u.indexR.rs1 = rs1; _i.u.indexR.rs2 = rs2; return _i; } /************** indirectR rs1 is (?noname?) i == 0 & rs2 == 0 & rs1 = rs1 ***********/ static regaddr_Instance indirectR(unsigned /* [0..31] */ rs1) { regaddr_Instance _i = { indirectR_TAG }; _i.u.indirectR.rs1 = rs1; return _i; } /************** LDSBA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 25 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 25 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDSBA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSBA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDSBA.regaddr = regaddr; _i.u.LDSBA.asi = asi; _i.u.LDSBA.rd = rd; return _i; } /************** LDSHA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 26 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 26 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDSHA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSHA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDSHA.regaddr = regaddr; _i.u.LDSHA.asi = asi; _i.u.LDSHA.rd = rd; return _i; } /************** LDUBA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 17 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 17 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDUBA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDUBA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDUBA.regaddr = regaddr; _i.u.LDUBA.asi = asi; _i.u.LDUBA.rd = rd; return _i; } /************** LDUHA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 18 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 18 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDUHA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDUHA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDUHA.regaddr = regaddr; _i.u.LDUHA.asi = asi; _i.u.LDUHA.rd = rd; return _i; } /************** LDA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 16 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 16 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDA.regaddr = regaddr; _i.u.LDA.asi = asi; _i.u.LDA.rd = rd; return _i; } /************** LDSTUBA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 29 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 29 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDSTUBA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDSTUBA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDSTUBA.regaddr = regaddr; _i.u.LDSTUBA.asi = asi; _i.u.LDSTUBA.rd = rd; return _i; } /************** SWAPA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 31 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 31 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance SWAPA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SWAPA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.SWAPA.regaddr = regaddr; _i.u.SWAPA.asi = asi; _i.u.SWAPA.rd = rd; return _i; } /************** LDDA [regaddr]asi, rd is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 19 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & asi = asi & rd = rd | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 19 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & asi = asi & rd = rd END (* regaddr *) ***********/ static instruction_Instance LDDA(regaddr_Instance regaddr, unsigned /* [0..255] */ asi, unsigned /* [0..31] */ rd) { instruction_Instance _i = { LDDA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.LDDA.regaddr = regaddr; _i.u.LDDA.asi = asi; _i.u.LDDA.rd = rd; return _i; } /************** STBA rd, [regaddr]asi is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 21 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & rd = rd & asi = asi | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 21 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & rd = rd & asi = asi END (* regaddr *) ***********/ static instruction_Instance STBA(unsigned /* [0..31] */ rd, regaddr_Instance regaddr, unsigned /* [0..255] */ asi) { instruction_Instance _i = { STBA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.STBA.rd = rd; _i.u.STBA.regaddr = regaddr; _i.u.STBA.asi = asi; return _i; } /************** STHA rd, [regaddr]asi is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 22 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & rd = rd & asi = asi | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 22 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & rd = rd & asi = asi END (* regaddr *) ***********/ static instruction_Instance STHA(unsigned /* [0..31] */ rd, regaddr_Instance regaddr, unsigned /* [0..255] */ asi) { instruction_Instance _i = { STHA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.STHA.rd = rd; _i.u.STHA.regaddr = regaddr; _i.u.STHA.asi = asi; return _i; } /************** STA rd, [regaddr]asi is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 20 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & rd = rd & asi = asi | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 20 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & rd = rd & asi = asi END (* regaddr *) ***********/ static instruction_Instance STA(unsigned /* [0..31] */ rd, regaddr_Instance regaddr, unsigned /* [0..255] */ asi) { instruction_Instance _i = { STA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.STA.rd = rd; _i.u.STA.regaddr = regaddr; _i.u.STA.asi = asi; return _i; } /************** STDA rd, [regaddr]asi is CASE regaddr OF | indexR => (?noname?) (?regaddr:): op == 3 & op3 == 23 & i == 0 & rs1 = regaddr.indexR.rs1 & rs2 = regaddr.indexR.rs2 & rd = rd & asi = asi | indirectR => (?noname?) (?regaddr:): op == 3 & op3 == 23 & i == 0 & rs2 == 0 & rs1 = regaddr.indirectR.rs1 & rd = rd & asi = asi END (* regaddr *) ***********/ static instruction_Instance STDA(unsigned /* [0..31] */ rd, regaddr_Instance regaddr, unsigned /* [0..255] */ asi) { instruction_Instance _i = { STDA_TAG }; if (!((unsigned)(asi) < 0x100)) (*fail) ("asi = %d won't fit in 8 unsigned bits"); _i.u.STDA.rd = rd; _i.u.STDA.regaddr = regaddr; _i.u.STDA.asi = asi; return _i; } /************** LDFSR [address_], %fsr is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 33 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 33 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 33 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 33 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 33 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 33 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance LDFSR(address__Instance address_) { instruction_Instance _i = { LDFSR_TAG }; _i.u.LDFSR.address_ = address_; return _i; } /************** LDCSR [address_], %csr is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 49 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 49 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 49 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 49 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 49 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 49 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance LDCSR(address__Instance address_) { instruction_Instance _i = { LDCSR_TAG }; _i.u.LDCSR.address_ = address_; return _i; } /************** STFSR %fsr, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 37 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 37 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 37 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 37 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 37 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 37 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance STFSR(address__Instance address_) { instruction_Instance _i = { STFSR_TAG }; _i.u.STFSR.address_ = address_; return _i; } /************** STCSR %csr, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 53 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 53 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 53 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 53 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 53 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 53 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance STCSR(address__Instance address_) { instruction_Instance _i = { STCSR_TAG }; _i.u.STCSR.address_ = address_; return _i; } /************** STDFQ %fq, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 38 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 38 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 38 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 38 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 38 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 38 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance STDFQ(address__Instance address_) { instruction_Instance _i = { STDFQ_TAG }; _i.u.STDFQ.address_ = address_; return _i; } /************** STDCQ %cq, [address_] is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 3 & op3 == 54 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 3 & op3 == 54 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 54 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 54 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 3 & op3 == 54 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 3 & op3 == 54 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance STDCQ(address__Instance address_) { instruction_Instance _i = { STDCQ_TAG }; _i.u.STDCQ.address_ = address_; return _i; } /************** RDY %y, rd is (RDY) op == 2 & op3 == 40 & rs1 == 0 & rd = rd ***********/ static instruction_Instance RDY(unsigned /* [0..31] */ rd) { instruction_Instance _i = { RDY_TAG }; _i.u.RDY.rd = rd; return _i; } /************** RDPSR %psr, rd is (RDPSR) op == 2 & op3 == 41 & rd = rd ***********/ static instruction_Instance RDPSR(unsigned /* [0..31] */ rd) { instruction_Instance _i = { RDPSR_TAG }; _i.u.RDPSR.rd = rd; return _i; } /************** RDWIM %wim, rd is (RDWIM) op == 2 & op3 == 42 & rd = rd ***********/ static instruction_Instance RDWIM(unsigned /* [0..31] */ rd) { instruction_Instance _i = { RDWIM_TAG }; _i.u.RDWIM.rd = rd; return _i; } /************** RDTBR %tbr, rd is (RDTBR) op == 2 & op3 == 43 & rd = rd ***********/ static instruction_Instance RDTBR(unsigned /* [0..31] */ rd) { instruction_Instance _i = { RDTBR_TAG }; _i.u.RDTBR.rd = rd; return _i; } /************** WRY rs1, reg_or_imm, %y is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 48 & rd == 0 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 48 & rd == 0 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 END (* reg_or_imm *) ***********/ static instruction_Instance WRY(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { instruction_Instance _i = { WRY_TAG }; _i.u.WRY.rs1 = rs1; _i.u.WRY.reg_or_imm = reg_or_imm; return _i; } /************** WRPSR rs1, reg_or_imm, %psr is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 49 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 49 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 END (* reg_or_imm *) ***********/ static instruction_Instance WRPSR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { instruction_Instance _i = { WRPSR_TAG }; _i.u.WRPSR.rs1 = rs1; _i.u.WRPSR.reg_or_imm = reg_or_imm; return _i; } /************** WRWIM rs1, reg_or_imm, %wim is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 50 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 50 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 END (* reg_or_imm *) ***********/ static instruction_Instance WRWIM(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { instruction_Instance _i = { WRWIM_TAG }; _i.u.WRWIM.rs1 = rs1; _i.u.WRWIM.reg_or_imm = reg_or_imm; return _i; } /************** WRTBR rs1, reg_or_imm, %tbr is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 51 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 51 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 END (* reg_or_imm *) ***********/ static instruction_Instance WRTBR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { instruction_Instance _i = { WRTBR_TAG }; _i.u.WRTBR.rs1 = rs1; _i.u.WRTBR.reg_or_imm = reg_or_imm; return _i; } /************** RDASR %asrrs1i, rd is (RDASR) op == 2 & op3 == 40 & 1 <= rs1 < 32 & rs1i = rs1i & rd = rd ***********/ static instruction_Instance RDASR(unsigned /* [0..31] */ rs1i, unsigned /* [0..31] */ rd) { instruction_Instance _i = { RDASR_TAG }; if (!((unsigned)(rs1i) < 0x20)) (*fail) ("rs1i = %d won't fit in 5 unsigned bits"); _i.u.RDASR.rs1i = rs1i; _i.u.RDASR.rd = rd; return _i; } /************** WRASR rs1, reg_or_imm, %asrrdi is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 48 & 1 <= rd < 32 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rdi = rdi | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 48 & 1 <= rd < 32 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rdi = rdi END (* reg_or_imm *) ***********/ static instruction_Instance WRASR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rdi) { instruction_Instance _i = { WRASR_TAG }; if (!((unsigned)(rdi) < 0x20)) (*fail) ("rdi = %d won't fit in 5 unsigned bits"); _i.u.WRASR.rs1 = rs1; _i.u.WRASR.reg_or_imm = reg_or_imm; _i.u.WRASR.rdi = rdi; return _i; } /************** STBAR is (STBAR) op == 2 & op3 == 40 & rs1 == 15 & rd == 0 ***********/ static instruction_Instance STBAR(void) { instruction_Instance _i = { STBAR_TAG }; return _i; } /************** AND rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 1 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 1 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance AND(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { AND_TAG }; _i.u.AND.rs1 = rs1; _i.u.AND.reg_or_imm = reg_or_imm; _i.u.AND.rd = rd; return _i; } /************** ANDcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 17 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 17 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ANDcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ANDcc_TAG }; _i.u.ANDcc.rs1 = rs1; _i.u.ANDcc.reg_or_imm = reg_or_imm; _i.u.ANDcc.rd = rd; return _i; } /************** ANDN rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 5 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 5 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ANDN(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ANDN_TAG }; _i.u.ANDN.rs1 = rs1; _i.u.ANDN.reg_or_imm = reg_or_imm; _i.u.ANDN.rd = rd; return _i; } /************** ANDNcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 21 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 21 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ANDNcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ANDNcc_TAG }; _i.u.ANDNcc.rs1 = rs1; _i.u.ANDNcc.reg_or_imm = reg_or_imm; _i.u.ANDNcc.rd = rd; return _i; } /************** OR rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 2 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 2 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance OR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { OR_TAG }; _i.u.OR.rs1 = rs1; _i.u.OR.reg_or_imm = reg_or_imm; _i.u.OR.rd = rd; return _i; } /************** ORcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 18 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 18 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ORcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ORcc_TAG }; _i.u.ORcc.rs1 = rs1; _i.u.ORcc.reg_or_imm = reg_or_imm; _i.u.ORcc.rd = rd; return _i; } /************** ORN rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 6 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 6 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ORN(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ORN_TAG }; _i.u.ORN.rs1 = rs1; _i.u.ORN.reg_or_imm = reg_or_imm; _i.u.ORN.rd = rd; return _i; } /************** ORNcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 22 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 22 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ORNcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ORNcc_TAG }; _i.u.ORNcc.rs1 = rs1; _i.u.ORNcc.reg_or_imm = reg_or_imm; _i.u.ORNcc.rd = rd; return _i; } /************** XOR rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 3 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 3 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance XOR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { XOR_TAG }; _i.u.XOR.rs1 = rs1; _i.u.XOR.reg_or_imm = reg_or_imm; _i.u.XOR.rd = rd; return _i; } /************** XORcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 19 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 19 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance XORcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { XORcc_TAG }; _i.u.XORcc.rs1 = rs1; _i.u.XORcc.reg_or_imm = reg_or_imm; _i.u.XORcc.rd = rd; return _i; } /************** XNOR rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 7 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 7 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance XNOR(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { XNOR_TAG }; _i.u.XNOR.rs1 = rs1; _i.u.XNOR.reg_or_imm = reg_or_imm; _i.u.XNOR.rd = rd; return _i; } /************** XNORcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 23 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 23 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance XNORcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { XNORcc_TAG }; _i.u.XNORcc.rs1 = rs1; _i.u.XNORcc.reg_or_imm = reg_or_imm; _i.u.XNORcc.rd = rd; return _i; } /************** SLL rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 37 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 37 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SLL(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SLL_TAG }; _i.u.SLL.rs1 = rs1; _i.u.SLL.reg_or_imm = reg_or_imm; _i.u.SLL.rd = rd; return _i; } /************** SRL rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 38 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 38 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SRL(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SRL_TAG }; _i.u.SRL.rs1 = rs1; _i.u.SRL.reg_or_imm = reg_or_imm; _i.u.SRL.rd = rd; return _i; } /************** SRA rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 39 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 39 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SRA(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SRA_TAG }; _i.u.SRA.rs1 = rs1; _i.u.SRA.reg_or_imm = reg_or_imm; _i.u.SRA.rd = rd; return _i; } /************** ADD rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 0 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 0 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ADD(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ADD_TAG }; _i.u.ADD.rs1 = rs1; _i.u.ADD.reg_or_imm = reg_or_imm; _i.u.ADD.rd = rd; return _i; } /************** ADDcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 16 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 16 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ADDcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ADDcc_TAG }; _i.u.ADDcc.rs1 = rs1; _i.u.ADDcc.reg_or_imm = reg_or_imm; _i.u.ADDcc.rd = rd; return _i; } /************** ADDX rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 8 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 8 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ADDX(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ADDX_TAG }; _i.u.ADDX.rs1 = rs1; _i.u.ADDX.reg_or_imm = reg_or_imm; _i.u.ADDX.rd = rd; return _i; } /************** ADDXcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 24 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 24 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance ADDXcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { ADDXcc_TAG }; _i.u.ADDXcc.rs1 = rs1; _i.u.ADDXcc.reg_or_imm = reg_or_imm; _i.u.ADDXcc.rd = rd; return _i; } /************** TADDcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 32 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 32 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance TADDcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { TADDcc_TAG }; _i.u.TADDcc.rs1 = rs1; _i.u.TADDcc.reg_or_imm = reg_or_imm; _i.u.TADDcc.rd = rd; return _i; } /************** TADDccTV rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 34 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 34 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance TADDccTV(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { TADDccTV_TAG }; _i.u.TADDccTV.rs1 = rs1; _i.u.TADDccTV.reg_or_imm = reg_or_imm; _i.u.TADDccTV.rd = rd; return _i; } /************** SUB rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 4 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 4 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SUB(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SUB_TAG }; _i.u.SUB.rs1 = rs1; _i.u.SUB.reg_or_imm = reg_or_imm; _i.u.SUB.rd = rd; return _i; } /************** SUBcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 20 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 20 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SUBcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SUBcc_TAG }; _i.u.SUBcc.rs1 = rs1; _i.u.SUBcc.reg_or_imm = reg_or_imm; _i.u.SUBcc.rd = rd; return _i; } /************** SUBX rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 12 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 12 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SUBX(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SUBX_TAG }; _i.u.SUBX.rs1 = rs1; _i.u.SUBX.reg_or_imm = reg_or_imm; _i.u.SUBX.rd = rd; return _i; } /************** SUBXcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 28 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 28 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SUBXcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SUBXcc_TAG }; _i.u.SUBXcc.rs1 = rs1; _i.u.SUBXcc.reg_or_imm = reg_or_imm; _i.u.SUBXcc.rd = rd; return _i; } /************** TSUBcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 33 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 33 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance TSUBcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { TSUBcc_TAG }; _i.u.TSUBcc.rs1 = rs1; _i.u.TSUBcc.reg_or_imm = reg_or_imm; _i.u.TSUBcc.rd = rd; return _i; } /************** TSUBccTV rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 35 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 35 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance TSUBccTV(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { TSUBccTV_TAG }; _i.u.TSUBccTV.rs1 = rs1; _i.u.TSUBccTV.reg_or_imm = reg_or_imm; _i.u.TSUBccTV.rd = rd; return _i; } /************** MULScc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 36 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 36 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance MULScc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { MULScc_TAG }; _i.u.MULScc.rs1 = rs1; _i.u.MULScc.reg_or_imm = reg_or_imm; _i.u.MULScc.rd = rd; return _i; } /************** UMUL rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 10 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 10 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance UMUL(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { UMUL_TAG }; _i.u.UMUL.rs1 = rs1; _i.u.UMUL.reg_or_imm = reg_or_imm; _i.u.UMUL.rd = rd; return _i; } /************** SMUL rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 11 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 11 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SMUL(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SMUL_TAG }; _i.u.SMUL.rs1 = rs1; _i.u.SMUL.reg_or_imm = reg_or_imm; _i.u.SMUL.rd = rd; return _i; } /************** UMULcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 26 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 26 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance UMULcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { UMULcc_TAG }; _i.u.UMULcc.rs1 = rs1; _i.u.UMULcc.reg_or_imm = reg_or_imm; _i.u.UMULcc.rd = rd; return _i; } /************** SMULcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 27 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 27 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SMULcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SMULcc_TAG }; _i.u.SMULcc.rs1 = rs1; _i.u.SMULcc.reg_or_imm = reg_or_imm; _i.u.SMULcc.rd = rd; return _i; } /************** UDIV rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 14 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 14 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance UDIV(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { UDIV_TAG }; _i.u.UDIV.rs1 = rs1; _i.u.UDIV.reg_or_imm = reg_or_imm; _i.u.UDIV.rd = rd; return _i; } /************** SDIV rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 15 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 15 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SDIV(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SDIV_TAG }; _i.u.SDIV.rs1 = rs1; _i.u.SDIV.reg_or_imm = reg_or_imm; _i.u.SDIV.rd = rd; return _i; } /************** UDIVcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 30 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 30 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance UDIVcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { UDIVcc_TAG }; _i.u.UDIVcc.rs1 = rs1; _i.u.UDIVcc.reg_or_imm = reg_or_imm; _i.u.UDIVcc.rd = rd; return _i; } /************** SDIVcc rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 31 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 31 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SDIVcc(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SDIVcc_TAG }; _i.u.SDIVcc.rs1 = rs1; _i.u.SDIVcc.reg_or_imm = reg_or_imm; _i.u.SDIVcc.rd = rd; return _i; } /************** SAVE rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 60 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 60 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance SAVE(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { SAVE_TAG }; _i.u.SAVE.rs1 = rs1; _i.u.SAVE.reg_or_imm = reg_or_imm; _i.u.SAVE.rd = rd; return _i; } /************** RESTORE rs1, reg_or_imm, rd is CASE reg_or_imm OF | imode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 61 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = rd | rmode => (?noname?) (?reg_or_imm:): op == 2 & op3 == 61 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance RESTORE(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { RESTORE_TAG }; _i.u.RESTORE.rs1 = rs1; _i.u.RESTORE.reg_or_imm = reg_or_imm; _i.u.RESTORE.rd = rd; return _i; } /************** BN reloc is (?noname?) {(reloc - LOCATION_OF(L#1:)) MOD 4 = 0} => L#1:: op == 0 & op2 == 2 & cond == 0 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#1:)) DIV 4)[22!] ***********/ static instruction_Instance BN(int reloc) { instruction_Instance _i = { BN_TAG }; _i.u.BN.reloc = reloc; return _i; } /************** BN_a reloc is (?noname?) {(reloc - LOCATION_OF(L#2:)) MOD 4 = 0} => L#2:: op == 0 & op2 == 2 & cond == 0 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#2:)) DIV 4)[22!] ***********/ static instruction_Instance BN_a(int reloc) { instruction_Instance _i = { BN_a_TAG }; _i.u.BN_a.reloc = reloc; return _i; } /************** BE reloc is (?noname?) {(reloc - LOCATION_OF(L#3:)) MOD 4 = 0} => L#3:: op == 0 & op2 == 2 & cond == 1 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#3:)) DIV 4)[22!] ***********/ static instruction_Instance BE(int reloc) { instruction_Instance _i = { BE_TAG }; _i.u.BE.reloc = reloc; return _i; } /************** BE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#4:)) MOD 4 = 0} => L#4:: op == 0 & op2 == 2 & cond == 1 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#4:)) DIV 4)[22!] ***********/ static instruction_Instance BE_a(int reloc) { instruction_Instance _i = { BE_a_TAG }; _i.u.BE_a.reloc = reloc; return _i; } /************** BLE reloc is (?noname?) {(reloc - LOCATION_OF(L#5:)) MOD 4 = 0} => L#5:: op == 0 & op2 == 2 & cond == 2 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#5:)) DIV 4)[22!] ***********/ static instruction_Instance BLE(int reloc) { instruction_Instance _i = { BLE_TAG }; _i.u.BLE.reloc = reloc; return _i; } /************** BLE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#6:)) MOD 4 = 0} => L#6:: op == 0 & op2 == 2 & cond == 2 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#6:)) DIV 4)[22!] ***********/ static instruction_Instance BLE_a(int reloc) { instruction_Instance _i = { BLE_a_TAG }; _i.u.BLE_a.reloc = reloc; return _i; } /************** BL reloc is (?noname?) {(reloc - LOCATION_OF(L#7:)) MOD 4 = 0} => L#7:: op == 0 & op2 == 2 & cond == 3 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#7:)) DIV 4)[22!] ***********/ static instruction_Instance BL(int reloc) { instruction_Instance _i = { BL_TAG }; _i.u.BL.reloc = reloc; return _i; } /************** BL_a reloc is (?noname?) {(reloc - LOCATION_OF(L#8:)) MOD 4 = 0} => L#8:: op == 0 & op2 == 2 & cond == 3 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#8:)) DIV 4)[22!] ***********/ static instruction_Instance BL_a(int reloc) { instruction_Instance _i = { BL_a_TAG }; _i.u.BL_a.reloc = reloc; return _i; } /************** BLEU reloc is (?noname?) {(reloc - LOCATION_OF(L#9:)) MOD 4 = 0} => L#9:: op == 0 & op2 == 2 & cond == 4 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#9:)) DIV 4)[22!] ***********/ static instruction_Instance BLEU(int reloc) { instruction_Instance _i = { BLEU_TAG }; _i.u.BLEU.reloc = reloc; return _i; } /************** BLEU_a reloc is (?noname?) {(reloc - LOCATION_OF(L#10:)) MOD 4 = 0} => L#10:: op == 0 & op2 == 2 & cond == 4 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#10:)) DIV 4)[22!] ***********/ static instruction_Instance BLEU_a(int reloc) { instruction_Instance _i = { BLEU_a_TAG }; _i.u.BLEU_a.reloc = reloc; return _i; } /************** BCS reloc is (?noname?) {(reloc - LOCATION_OF(L#11:)) MOD 4 = 0} => L#11:: op == 0 & op2 == 2 & cond == 5 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#11:)) DIV 4)[22!] ***********/ static instruction_Instance BCS(int reloc) { instruction_Instance _i = { BCS_TAG }; _i.u.BCS.reloc = reloc; return _i; } /************** BCS_a reloc is (?noname?) {(reloc - LOCATION_OF(L#12:)) MOD 4 = 0} => L#12:: op == 0 & op2 == 2 & cond == 5 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#12:)) DIV 4)[22!] ***********/ static instruction_Instance BCS_a(int reloc) { instruction_Instance _i = { BCS_a_TAG }; _i.u.BCS_a.reloc = reloc; return _i; } /************** BNEG reloc is (?noname?) {(reloc - LOCATION_OF(L#13:)) MOD 4 = 0} => L#13:: op == 0 & op2 == 2 & cond == 6 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#13:)) DIV 4)[22!] ***********/ static instruction_Instance BNEG(int reloc) { instruction_Instance _i = { BNEG_TAG }; _i.u.BNEG.reloc = reloc; return _i; } /************** BNEG_a reloc is (?noname?) {(reloc - LOCATION_OF(L#14:)) MOD 4 = 0} => L#14:: op == 0 & op2 == 2 & cond == 6 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#14:)) DIV 4)[22!] ***********/ static instruction_Instance BNEG_a(int reloc) { instruction_Instance _i = { BNEG_a_TAG }; _i.u.BNEG_a.reloc = reloc; return _i; } /************** BVS reloc is (?noname?) {(reloc - LOCATION_OF(L#15:)) MOD 4 = 0} => L#15:: op == 0 & op2 == 2 & cond == 7 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#15:)) DIV 4)[22!] ***********/ static instruction_Instance BVS(int reloc) { instruction_Instance _i = { BVS_TAG }; _i.u.BVS.reloc = reloc; return _i; } /************** BVS_a reloc is (?noname?) {(reloc - LOCATION_OF(L#16:)) MOD 4 = 0} => L#16:: op == 0 & op2 == 2 & cond == 7 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#16:)) DIV 4)[22!] ***********/ static instruction_Instance BVS_a(int reloc) { instruction_Instance _i = { BVS_a_TAG }; _i.u.BVS_a.reloc = reloc; return _i; } /************** BA reloc is (?noname?) {(reloc - LOCATION_OF(L#17:)) MOD 4 = 0} => L#17:: op == 0 & op2 == 2 & cond == 8 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#17:)) DIV 4)[22!] ***********/ static instruction_Instance BA(int reloc) { instruction_Instance _i = { BA_TAG }; _i.u.BA.reloc = reloc; return _i; } /************** BA_a reloc is (?noname?) {(reloc - LOCATION_OF(L#18:)) MOD 4 = 0} => L#18:: op == 0 & op2 == 2 & cond == 8 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#18:)) DIV 4)[22!] ***********/ static instruction_Instance BA_a(int reloc) { instruction_Instance _i = { BA_a_TAG }; _i.u.BA_a.reloc = reloc; return _i; } /************** BNE reloc is (?noname?) {(reloc - LOCATION_OF(L#19:)) MOD 4 = 0} => L#19:: op == 0 & op2 == 2 & cond == 9 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#19:)) DIV 4)[22!] ***********/ static instruction_Instance BNE(int reloc) { instruction_Instance _i = { BNE_TAG }; _i.u.BNE.reloc = reloc; return _i; } /************** BNE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#20:)) MOD 4 = 0} => L#20:: op == 0 & op2 == 2 & cond == 9 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#20:)) DIV 4)[22!] ***********/ static instruction_Instance BNE_a(int reloc) { instruction_Instance _i = { BNE_a_TAG }; _i.u.BNE_a.reloc = reloc; return _i; } /************** BG reloc is (?noname?) {(reloc - LOCATION_OF(L#21:)) MOD 4 = 0} => L#21:: op == 0 & op2 == 2 & cond == 10 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#21:)) DIV 4)[22!] ***********/ static instruction_Instance BG(int reloc) { instruction_Instance _i = { BG_TAG }; _i.u.BG.reloc = reloc; return _i; } /************** BG_a reloc is (?noname?) {(reloc - LOCATION_OF(L#22:)) MOD 4 = 0} => L#22:: op == 0 & op2 == 2 & cond == 10 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#22:)) DIV 4)[22!] ***********/ static instruction_Instance BG_a(int reloc) { instruction_Instance _i = { BG_a_TAG }; _i.u.BG_a.reloc = reloc; return _i; } /************** BGE reloc is (?noname?) {(reloc - LOCATION_OF(L#23:)) MOD 4 = 0} => L#23:: op == 0 & op2 == 2 & cond == 11 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#23:)) DIV 4)[22!] ***********/ static instruction_Instance BGE(int reloc) { instruction_Instance _i = { BGE_TAG }; _i.u.BGE.reloc = reloc; return _i; } /************** BGE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#24:)) MOD 4 = 0} => L#24:: op == 0 & op2 == 2 & cond == 11 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#24:)) DIV 4)[22!] ***********/ static instruction_Instance BGE_a(int reloc) { instruction_Instance _i = { BGE_a_TAG }; _i.u.BGE_a.reloc = reloc; return _i; } /************** BGU reloc is (?noname?) {(reloc - LOCATION_OF(L#25:)) MOD 4 = 0} => L#25:: op == 0 & op2 == 2 & cond == 12 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#25:)) DIV 4)[22!] ***********/ static instruction_Instance BGU(int reloc) { instruction_Instance _i = { BGU_TAG }; _i.u.BGU.reloc = reloc; return _i; } /************** BGU_a reloc is (?noname?) {(reloc - LOCATION_OF(L#26:)) MOD 4 = 0} => L#26:: op == 0 & op2 == 2 & cond == 12 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#26:)) DIV 4)[22!] ***********/ static instruction_Instance BGU_a(int reloc) { instruction_Instance _i = { BGU_a_TAG }; _i.u.BGU_a.reloc = reloc; return _i; } /************** BCC reloc is (?noname?) {(reloc - LOCATION_OF(L#27:)) MOD 4 = 0} => L#27:: op == 0 & op2 == 2 & cond == 13 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#27:)) DIV 4)[22!] ***********/ static instruction_Instance BCC(int reloc) { instruction_Instance _i = { BCC_TAG }; _i.u.BCC.reloc = reloc; return _i; } /************** BCC_a reloc is (?noname?) {(reloc - LOCATION_OF(L#28:)) MOD 4 = 0} => L#28:: op == 0 & op2 == 2 & cond == 13 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#28:)) DIV 4)[22!] ***********/ static instruction_Instance BCC_a(int reloc) { instruction_Instance _i = { BCC_a_TAG }; _i.u.BCC_a.reloc = reloc; return _i; } /************** BPOS reloc is (?noname?) {(reloc - LOCATION_OF(L#29:)) MOD 4 = 0} => L#29:: op == 0 & op2 == 2 & cond == 14 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#29:)) DIV 4)[22!] ***********/ static instruction_Instance BPOS(int reloc) { instruction_Instance _i = { BPOS_TAG }; _i.u.BPOS.reloc = reloc; return _i; } /************** BPOS_a reloc is (?noname?) {(reloc - LOCATION_OF(L#30:)) MOD 4 = 0} => L#30:: op == 0 & op2 == 2 & cond == 14 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#30:)) DIV 4)[22!] ***********/ static instruction_Instance BPOS_a(int reloc) { instruction_Instance _i = { BPOS_a_TAG }; _i.u.BPOS_a.reloc = reloc; return _i; } /************** BVC reloc is (?noname?) {(reloc - LOCATION_OF(L#31:)) MOD 4 = 0} => L#31:: op == 0 & op2 == 2 & cond == 15 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#31:)) DIV 4)[22!] ***********/ static instruction_Instance BVC(int reloc) { instruction_Instance _i = { BVC_TAG }; _i.u.BVC.reloc = reloc; return _i; } /************** BVC_a reloc is (?noname?) {(reloc - LOCATION_OF(L#32:)) MOD 4 = 0} => L#32:: op == 0 & op2 == 2 & cond == 15 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#32:)) DIV 4)[22!] ***********/ static instruction_Instance BVC_a(int reloc) { instruction_Instance _i = { BVC_a_TAG }; _i.u.BVC_a.reloc = reloc; return _i; } /************** FBN reloc is (?noname?) {(reloc - LOCATION_OF(L#33:)) MOD 4 = 0} => L#33:: op == 0 & op2 == 6 & cond == 0 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#33:)) DIV 4)[22!] ***********/ static instruction_Instance FBN(int reloc) { instruction_Instance _i = { FBN_TAG }; _i.u.FBN.reloc = reloc; return _i; } /************** FBN_a reloc is (?noname?) {(reloc - LOCATION_OF(L#34:)) MOD 4 = 0} => L#34:: op == 0 & op2 == 6 & cond == 0 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#34:)) DIV 4)[22!] ***********/ static instruction_Instance FBN_a(int reloc) { instruction_Instance _i = { FBN_a_TAG }; _i.u.FBN_a.reloc = reloc; return _i; } /************** FBNE reloc is (?noname?) {(reloc - LOCATION_OF(L#35:)) MOD 4 = 0} => L#35:: op == 0 & op2 == 6 & cond == 1 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#35:)) DIV 4)[22!] ***********/ static instruction_Instance FBNE(int reloc) { instruction_Instance _i = { FBNE_TAG }; _i.u.FBNE.reloc = reloc; return _i; } /************** FBNE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#36:)) MOD 4 = 0} => L#36:: op == 0 & op2 == 6 & cond == 1 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#36:)) DIV 4)[22!] ***********/ static instruction_Instance FBNE_a(int reloc) { instruction_Instance _i = { FBNE_a_TAG }; _i.u.FBNE_a.reloc = reloc; return _i; } /************** FBLG reloc is (?noname?) {(reloc - LOCATION_OF(L#37:)) MOD 4 = 0} => L#37:: op == 0 & op2 == 6 & cond == 2 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#37:)) DIV 4)[22!] ***********/ static instruction_Instance FBLG(int reloc) { instruction_Instance _i = { FBLG_TAG }; _i.u.FBLG.reloc = reloc; return _i; } /************** FBLG_a reloc is (?noname?) {(reloc - LOCATION_OF(L#38:)) MOD 4 = 0} => L#38:: op == 0 & op2 == 6 & cond == 2 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#38:)) DIV 4)[22!] ***********/ static instruction_Instance FBLG_a(int reloc) { instruction_Instance _i = { FBLG_a_TAG }; _i.u.FBLG_a.reloc = reloc; return _i; } /************** FBUL reloc is (?noname?) {(reloc - LOCATION_OF(L#39:)) MOD 4 = 0} => L#39:: op == 0 & op2 == 6 & cond == 3 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#39:)) DIV 4)[22!] ***********/ static instruction_Instance FBUL(int reloc) { instruction_Instance _i = { FBUL_TAG }; _i.u.FBUL.reloc = reloc; return _i; } /************** FBUL_a reloc is (?noname?) {(reloc - LOCATION_OF(L#40:)) MOD 4 = 0} => L#40:: op == 0 & op2 == 6 & cond == 3 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#40:)) DIV 4)[22!] ***********/ static instruction_Instance FBUL_a(int reloc) { instruction_Instance _i = { FBUL_a_TAG }; _i.u.FBUL_a.reloc = reloc; return _i; } /************** FBL reloc is (?noname?) {(reloc - LOCATION_OF(L#41:)) MOD 4 = 0} => L#41:: op == 0 & op2 == 6 & cond == 4 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#41:)) DIV 4)[22!] ***********/ static instruction_Instance FBL(int reloc) { instruction_Instance _i = { FBL_TAG }; _i.u.FBL.reloc = reloc; return _i; } /************** FBL_a reloc is (?noname?) {(reloc - LOCATION_OF(L#42:)) MOD 4 = 0} => L#42:: op == 0 & op2 == 6 & cond == 4 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#42:)) DIV 4)[22!] ***********/ static instruction_Instance FBL_a(int reloc) { instruction_Instance _i = { FBL_a_TAG }; _i.u.FBL_a.reloc = reloc; return _i; } /************** FBUG reloc is (?noname?) {(reloc - LOCATION_OF(L#43:)) MOD 4 = 0} => L#43:: op == 0 & op2 == 6 & cond == 5 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#43:)) DIV 4)[22!] ***********/ static instruction_Instance FBUG(int reloc) { instruction_Instance _i = { FBUG_TAG }; _i.u.FBUG.reloc = reloc; return _i; } /************** FBUG_a reloc is (?noname?) {(reloc - LOCATION_OF(L#44:)) MOD 4 = 0} => L#44:: op == 0 & op2 == 6 & cond == 5 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#44:)) DIV 4)[22!] ***********/ static instruction_Instance FBUG_a(int reloc) { instruction_Instance _i = { FBUG_a_TAG }; _i.u.FBUG_a.reloc = reloc; return _i; } /************** FBG reloc is (?noname?) {(reloc - LOCATION_OF(L#45:)) MOD 4 = 0} => L#45:: op == 0 & op2 == 6 & cond == 6 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#45:)) DIV 4)[22!] ***********/ static instruction_Instance FBG(int reloc) { instruction_Instance _i = { FBG_TAG }; _i.u.FBG.reloc = reloc; return _i; } /************** FBG_a reloc is (?noname?) {(reloc - LOCATION_OF(L#46:)) MOD 4 = 0} => L#46:: op == 0 & op2 == 6 & cond == 6 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#46:)) DIV 4)[22!] ***********/ static instruction_Instance FBG_a(int reloc) { instruction_Instance _i = { FBG_a_TAG }; _i.u.FBG_a.reloc = reloc; return _i; } /************** FBU reloc is (?noname?) {(reloc - LOCATION_OF(L#47:)) MOD 4 = 0} => L#47:: op == 0 & op2 == 6 & cond == 7 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#47:)) DIV 4)[22!] ***********/ static instruction_Instance FBU(int reloc) { instruction_Instance _i = { FBU_TAG }; _i.u.FBU.reloc = reloc; return _i; } /************** FBU_a reloc is (?noname?) {(reloc - LOCATION_OF(L#48:)) MOD 4 = 0} => L#48:: op == 0 & op2 == 6 & cond == 7 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#48:)) DIV 4)[22!] ***********/ static instruction_Instance FBU_a(int reloc) { instruction_Instance _i = { FBU_a_TAG }; _i.u.FBU_a.reloc = reloc; return _i; } /************** FBA reloc is (?noname?) {(reloc - LOCATION_OF(L#49:)) MOD 4 = 0} => L#49:: op == 0 & op2 == 6 & cond == 8 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#49:)) DIV 4)[22!] ***********/ static instruction_Instance FBA(int reloc) { instruction_Instance _i = { FBA_TAG }; _i.u.FBA.reloc = reloc; return _i; } /************** FBA_a reloc is (?noname?) {(reloc - LOCATION_OF(L#50:)) MOD 4 = 0} => L#50:: op == 0 & op2 == 6 & cond == 8 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#50:)) DIV 4)[22!] ***********/ static instruction_Instance FBA_a(int reloc) { instruction_Instance _i = { FBA_a_TAG }; _i.u.FBA_a.reloc = reloc; return _i; } /************** FBE reloc is (?noname?) {(reloc - LOCATION_OF(L#51:)) MOD 4 = 0} => L#51:: op == 0 & op2 == 6 & cond == 9 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#51:)) DIV 4)[22!] ***********/ static instruction_Instance FBE(int reloc) { instruction_Instance _i = { FBE_TAG }; _i.u.FBE.reloc = reloc; return _i; } /************** FBE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#52:)) MOD 4 = 0} => L#52:: op == 0 & op2 == 6 & cond == 9 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#52:)) DIV 4)[22!] ***********/ static instruction_Instance FBE_a(int reloc) { instruction_Instance _i = { FBE_a_TAG }; _i.u.FBE_a.reloc = reloc; return _i; } /************** FBUE reloc is (?noname?) {(reloc - LOCATION_OF(L#53:)) MOD 4 = 0} => L#53:: op == 0 & op2 == 6 & cond == 10 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#53:)) DIV 4)[22!] ***********/ static instruction_Instance FBUE(int reloc) { instruction_Instance _i = { FBUE_TAG }; _i.u.FBUE.reloc = reloc; return _i; } /************** FBUE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#54:)) MOD 4 = 0} => L#54:: op == 0 & op2 == 6 & cond == 10 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#54:)) DIV 4)[22!] ***********/ static instruction_Instance FBUE_a(int reloc) { instruction_Instance _i = { FBUE_a_TAG }; _i.u.FBUE_a.reloc = reloc; return _i; } /************** FBGE reloc is (?noname?) {(reloc - LOCATION_OF(L#55:)) MOD 4 = 0} => L#55:: op == 0 & op2 == 6 & cond == 11 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#55:)) DIV 4)[22!] ***********/ static instruction_Instance FBGE(int reloc) { instruction_Instance _i = { FBGE_TAG }; _i.u.FBGE.reloc = reloc; return _i; } /************** FBGE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#56:)) MOD 4 = 0} => L#56:: op == 0 & op2 == 6 & cond == 11 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#56:)) DIV 4)[22!] ***********/ static instruction_Instance FBGE_a(int reloc) { instruction_Instance _i = { FBGE_a_TAG }; _i.u.FBGE_a.reloc = reloc; return _i; } /************** FBUGE reloc is (?noname?) {(reloc - LOCATION_OF(L#57:)) MOD 4 = 0} => L#57:: op == 0 & op2 == 6 & cond == 12 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#57:)) DIV 4)[22!] ***********/ static instruction_Instance FBUGE(int reloc) { instruction_Instance _i = { FBUGE_TAG }; _i.u.FBUGE.reloc = reloc; return _i; } /************** FBUGE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#58:)) MOD 4 = 0} => L#58:: op == 0 & op2 == 6 & cond == 12 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#58:)) DIV 4)[22!] ***********/ static instruction_Instance FBUGE_a(int reloc) { instruction_Instance _i = { FBUGE_a_TAG }; _i.u.FBUGE_a.reloc = reloc; return _i; } /************** FBLE reloc is (?noname?) {(reloc - LOCATION_OF(L#59:)) MOD 4 = 0} => L#59:: op == 0 & op2 == 6 & cond == 13 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#59:)) DIV 4)[22!] ***********/ static instruction_Instance FBLE(int reloc) { instruction_Instance _i = { FBLE_TAG }; _i.u.FBLE.reloc = reloc; return _i; } /************** FBLE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#60:)) MOD 4 = 0} => L#60:: op == 0 & op2 == 6 & cond == 13 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#60:)) DIV 4)[22!] ***********/ static instruction_Instance FBLE_a(int reloc) { instruction_Instance _i = { FBLE_a_TAG }; _i.u.FBLE_a.reloc = reloc; return _i; } /************** FBULE reloc is (?noname?) {(reloc - LOCATION_OF(L#61:)) MOD 4 = 0} => L#61:: op == 0 & op2 == 6 & cond == 14 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#61:)) DIV 4)[22!] ***********/ static instruction_Instance FBULE(int reloc) { instruction_Instance _i = { FBULE_TAG }; _i.u.FBULE.reloc = reloc; return _i; } /************** FBULE_a reloc is (?noname?) {(reloc - LOCATION_OF(L#62:)) MOD 4 = 0} => L#62:: op == 0 & op2 == 6 & cond == 14 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#62:)) DIV 4)[22!] ***********/ static instruction_Instance FBULE_a(int reloc) { instruction_Instance _i = { FBULE_a_TAG }; _i.u.FBULE_a.reloc = reloc; return _i; } /************** FBO reloc is (?noname?) {(reloc - LOCATION_OF(L#63:)) MOD 4 = 0} => L#63:: op == 0 & op2 == 6 & cond == 15 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#63:)) DIV 4)[22!] ***********/ static instruction_Instance FBO(int reloc) { instruction_Instance _i = { FBO_TAG }; _i.u.FBO.reloc = reloc; return _i; } /************** FBO_a reloc is (?noname?) {(reloc - LOCATION_OF(L#64:)) MOD 4 = 0} => L#64:: op == 0 & op2 == 6 & cond == 15 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#64:)) DIV 4)[22!] ***********/ static instruction_Instance FBO_a(int reloc) { instruction_Instance _i = { FBO_a_TAG }; _i.u.FBO_a.reloc = reloc; return _i; } /************** CBN reloc is (?noname?) {(reloc - LOCATION_OF(L#65:)) MOD 4 = 0} => L#65:: op == 0 & op2 == 7 & cond == 0 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#65:)) DIV 4)[22!] ***********/ static instruction_Instance CBN(int reloc) { instruction_Instance _i = { CBN_TAG }; _i.u.CBN.reloc = reloc; return _i; } /************** CBN_a reloc is (?noname?) {(reloc - LOCATION_OF(L#66:)) MOD 4 = 0} => L#66:: op == 0 & op2 == 7 & cond == 0 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#66:)) DIV 4)[22!] ***********/ static instruction_Instance CBN_a(int reloc) { instruction_Instance _i = { CBN_a_TAG }; _i.u.CBN_a.reloc = reloc; return _i; } /************** CB123 reloc is (?noname?) {(reloc - LOCATION_OF(L#67:)) MOD 4 = 0} => L#67:: op == 0 & op2 == 7 & cond == 1 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#67:)) DIV 4)[22!] ***********/ static instruction_Instance CB123(int reloc) { instruction_Instance _i = { CB123_TAG }; _i.u.CB123.reloc = reloc; return _i; } /************** CB123_a reloc is (?noname?) {(reloc - LOCATION_OF(L#68:)) MOD 4 = 0} => L#68:: op == 0 & op2 == 7 & cond == 1 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#68:)) DIV 4)[22!] ***********/ static instruction_Instance CB123_a(int reloc) { instruction_Instance _i = { CB123_a_TAG }; _i.u.CB123_a.reloc = reloc; return _i; } /************** CB12 reloc is (?noname?) {(reloc - LOCATION_OF(L#69:)) MOD 4 = 0} => L#69:: op == 0 & op2 == 7 & cond == 2 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#69:)) DIV 4)[22!] ***********/ static instruction_Instance CB12(int reloc) { instruction_Instance _i = { CB12_TAG }; _i.u.CB12.reloc = reloc; return _i; } /************** CB12_a reloc is (?noname?) {(reloc - LOCATION_OF(L#70:)) MOD 4 = 0} => L#70:: op == 0 & op2 == 7 & cond == 2 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#70:)) DIV 4)[22!] ***********/ static instruction_Instance CB12_a(int reloc) { instruction_Instance _i = { CB12_a_TAG }; _i.u.CB12_a.reloc = reloc; return _i; } /************** CB13 reloc is (?noname?) {(reloc - LOCATION_OF(L#71:)) MOD 4 = 0} => L#71:: op == 0 & op2 == 7 & cond == 3 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#71:)) DIV 4)[22!] ***********/ static instruction_Instance CB13(int reloc) { instruction_Instance _i = { CB13_TAG }; _i.u.CB13.reloc = reloc; return _i; } /************** CB13_a reloc is (?noname?) {(reloc - LOCATION_OF(L#72:)) MOD 4 = 0} => L#72:: op == 0 & op2 == 7 & cond == 3 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#72:)) DIV 4)[22!] ***********/ static instruction_Instance CB13_a(int reloc) { instruction_Instance _i = { CB13_a_TAG }; _i.u.CB13_a.reloc = reloc; return _i; } /************** CB1 reloc is (?noname?) {(reloc - LOCATION_OF(L#73:)) MOD 4 = 0} => L#73:: op == 0 & op2 == 7 & cond == 4 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#73:)) DIV 4)[22!] ***********/ static instruction_Instance CB1(int reloc) { instruction_Instance _i = { CB1_TAG }; _i.u.CB1.reloc = reloc; return _i; } /************** CB1_a reloc is (?noname?) {(reloc - LOCATION_OF(L#74:)) MOD 4 = 0} => L#74:: op == 0 & op2 == 7 & cond == 4 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#74:)) DIV 4)[22!] ***********/ static instruction_Instance CB1_a(int reloc) { instruction_Instance _i = { CB1_a_TAG }; _i.u.CB1_a.reloc = reloc; return _i; } /************** CB23 reloc is (?noname?) {(reloc - LOCATION_OF(L#75:)) MOD 4 = 0} => L#75:: op == 0 & op2 == 7 & cond == 5 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#75:)) DIV 4)[22!] ***********/ static instruction_Instance CB23(int reloc) { instruction_Instance _i = { CB23_TAG }; _i.u.CB23.reloc = reloc; return _i; } /************** CB23_a reloc is (?noname?) {(reloc - LOCATION_OF(L#76:)) MOD 4 = 0} => L#76:: op == 0 & op2 == 7 & cond == 5 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#76:)) DIV 4)[22!] ***********/ static instruction_Instance CB23_a(int reloc) { instruction_Instance _i = { CB23_a_TAG }; _i.u.CB23_a.reloc = reloc; return _i; } /************** CB2 reloc is (?noname?) {(reloc - LOCATION_OF(L#77:)) MOD 4 = 0} => L#77:: op == 0 & op2 == 7 & cond == 6 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#77:)) DIV 4)[22!] ***********/ static instruction_Instance CB2(int reloc) { instruction_Instance _i = { CB2_TAG }; _i.u.CB2.reloc = reloc; return _i; } /************** CB2_a reloc is (?noname?) {(reloc - LOCATION_OF(L#78:)) MOD 4 = 0} => L#78:: op == 0 & op2 == 7 & cond == 6 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#78:)) DIV 4)[22!] ***********/ static instruction_Instance CB2_a(int reloc) { instruction_Instance _i = { CB2_a_TAG }; _i.u.CB2_a.reloc = reloc; return _i; } /************** CB3 reloc is (?noname?) {(reloc - LOCATION_OF(L#79:)) MOD 4 = 0} => L#79:: op == 0 & op2 == 7 & cond == 7 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#79:)) DIV 4)[22!] ***********/ static instruction_Instance CB3(int reloc) { instruction_Instance _i = { CB3_TAG }; _i.u.CB3.reloc = reloc; return _i; } /************** CB3_a reloc is (?noname?) {(reloc - LOCATION_OF(L#80:)) MOD 4 = 0} => L#80:: op == 0 & op2 == 7 & cond == 7 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#80:)) DIV 4)[22!] ***********/ static instruction_Instance CB3_a(int reloc) { instruction_Instance _i = { CB3_a_TAG }; _i.u.CB3_a.reloc = reloc; return _i; } /************** CBA reloc is (?noname?) {(reloc - LOCATION_OF(L#81:)) MOD 4 = 0} => L#81:: op == 0 & op2 == 7 & cond == 8 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#81:)) DIV 4)[22!] ***********/ static instruction_Instance CBA(int reloc) { instruction_Instance _i = { CBA_TAG }; _i.u.CBA.reloc = reloc; return _i; } /************** CBA_a reloc is (?noname?) {(reloc - LOCATION_OF(L#82:)) MOD 4 = 0} => L#82:: op == 0 & op2 == 7 & cond == 8 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#82:)) DIV 4)[22!] ***********/ static instruction_Instance CBA_a(int reloc) { instruction_Instance _i = { CBA_a_TAG }; _i.u.CBA_a.reloc = reloc; return _i; } /************** CB0 reloc is (?noname?) {(reloc - LOCATION_OF(L#83:)) MOD 4 = 0} => L#83:: op == 0 & op2 == 7 & cond == 9 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#83:)) DIV 4)[22!] ***********/ static instruction_Instance CB0(int reloc) { instruction_Instance _i = { CB0_TAG }; _i.u.CB0.reloc = reloc; return _i; } /************** CB0_a reloc is (?noname?) {(reloc - LOCATION_OF(L#84:)) MOD 4 = 0} => L#84:: op == 0 & op2 == 7 & cond == 9 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#84:)) DIV 4)[22!] ***********/ static instruction_Instance CB0_a(int reloc) { instruction_Instance _i = { CB0_a_TAG }; _i.u.CB0_a.reloc = reloc; return _i; } /************** CB03 reloc is (?noname?) {(reloc - LOCATION_OF(L#85:)) MOD 4 = 0} => L#85:: op == 0 & op2 == 7 & cond == 10 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#85:)) DIV 4)[22!] ***********/ static instruction_Instance CB03(int reloc) { instruction_Instance _i = { CB03_TAG }; _i.u.CB03.reloc = reloc; return _i; } /************** CB03_a reloc is (?noname?) {(reloc - LOCATION_OF(L#86:)) MOD 4 = 0} => L#86:: op == 0 & op2 == 7 & cond == 10 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#86:)) DIV 4)[22!] ***********/ static instruction_Instance CB03_a(int reloc) { instruction_Instance _i = { CB03_a_TAG }; _i.u.CB03_a.reloc = reloc; return _i; } /************** CB02 reloc is (?noname?) {(reloc - LOCATION_OF(L#87:)) MOD 4 = 0} => L#87:: op == 0 & op2 == 7 & cond == 11 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#87:)) DIV 4)[22!] ***********/ static instruction_Instance CB02(int reloc) { instruction_Instance _i = { CB02_TAG }; _i.u.CB02.reloc = reloc; return _i; } /************** CB02_a reloc is (?noname?) {(reloc - LOCATION_OF(L#88:)) MOD 4 = 0} => L#88:: op == 0 & op2 == 7 & cond == 11 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#88:)) DIV 4)[22!] ***********/ static instruction_Instance CB02_a(int reloc) { instruction_Instance _i = { CB02_a_TAG }; _i.u.CB02_a.reloc = reloc; return _i; } /************** CB023 reloc is (?noname?) {(reloc - LOCATION_OF(L#89:)) MOD 4 = 0} => L#89:: op == 0 & op2 == 7 & cond == 12 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#89:)) DIV 4)[22!] ***********/ static instruction_Instance CB023(int reloc) { instruction_Instance _i = { CB023_TAG }; _i.u.CB023.reloc = reloc; return _i; } /************** CB023_a reloc is (?noname?) {(reloc - LOCATION_OF(L#90:)) MOD 4 = 0} => L#90:: op == 0 & op2 == 7 & cond == 12 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#90:)) DIV 4)[22!] ***********/ static instruction_Instance CB023_a(int reloc) { instruction_Instance _i = { CB023_a_TAG }; _i.u.CB023_a.reloc = reloc; return _i; } /************** CB01 reloc is (?noname?) {(reloc - LOCATION_OF(L#91:)) MOD 4 = 0} => L#91:: op == 0 & op2 == 7 & cond == 13 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#91:)) DIV 4)[22!] ***********/ static instruction_Instance CB01(int reloc) { instruction_Instance _i = { CB01_TAG }; _i.u.CB01.reloc = reloc; return _i; } /************** CB01_a reloc is (?noname?) {(reloc - LOCATION_OF(L#92:)) MOD 4 = 0} => L#92:: op == 0 & op2 == 7 & cond == 13 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#92:)) DIV 4)[22!] ***********/ static instruction_Instance CB01_a(int reloc) { instruction_Instance _i = { CB01_a_TAG }; _i.u.CB01_a.reloc = reloc; return _i; } /************** CB013 reloc is (?noname?) {(reloc - LOCATION_OF(L#93:)) MOD 4 = 0} => L#93:: op == 0 & op2 == 7 & cond == 14 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#93:)) DIV 4)[22!] ***********/ static instruction_Instance CB013(int reloc) { instruction_Instance _i = { CB013_TAG }; _i.u.CB013.reloc = reloc; return _i; } /************** CB013_a reloc is (?noname?) {(reloc - LOCATION_OF(L#94:)) MOD 4 = 0} => L#94:: op == 0 & op2 == 7 & cond == 14 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#94:)) DIV 4)[22!] ***********/ static instruction_Instance CB013_a(int reloc) { instruction_Instance _i = { CB013_a_TAG }; _i.u.CB013_a.reloc = reloc; return _i; } /************** CB012 reloc is (?noname?) {(reloc - LOCATION_OF(L#95:)) MOD 4 = 0} => L#95:: op == 0 & op2 == 7 & cond == 15 & a == 0 & disp22 = ((reloc - LOCATION_OF(L#95:)) DIV 4)[22!] ***********/ static instruction_Instance CB012(int reloc) { instruction_Instance _i = { CB012_TAG }; _i.u.CB012.reloc = reloc; return _i; } /************** CB012_a reloc is (?noname?) {(reloc - LOCATION_OF(L#96:)) MOD 4 = 0} => L#96:: op == 0 & op2 == 7 & cond == 15 & a == 1 & disp22 = ((reloc - LOCATION_OF(L#96:)) DIV 4)[22!] ***********/ static instruction_Instance CB012_a(int reloc) { instruction_Instance _i = { CB012_a_TAG }; _i.u.CB012_a.reloc = reloc; return _i; } /************** call reloc is (?noname?) {(reloc - LOCATION_OF(L#97:)) MOD 4 = 0} => L#97:: op == 1 & disp30 = ((reloc - LOCATION_OF(L#97:)) DIV 4)[30!] ***********/ static instruction_Instance call(int reloc) { instruction_Instance _i = { call_TAG }; _i.u.call.reloc = reloc; return _i; } /************** FMOVs fs2, fd is (FMOVs) op == 2 & op3 == 52 & opf == 1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FMOVs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FMOVs_TAG }; _i.u.FMOVs.fs2 = fs2; _i.u.FMOVs.fd = fd; return _i; } /************** FNEGs fs2, fd is (FNEGs) op == 2 & op3 == 52 & opf == 5 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FNEGs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FNEGs_TAG }; _i.u.FNEGs.fs2 = fs2; _i.u.FNEGs.fd = fd; return _i; } /************** FABSs fs2, fd is (FABSs) op == 2 & op3 == 52 & opf == 9 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FABSs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FABSs_TAG }; _i.u.FABSs.fs2 = fs2; _i.u.FABSs.fd = fd; return _i; } /************** FSQRTs fs2, fd is (FSQRTs) op == 2 & op3 == 52 & opf == 41 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSQRTs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSQRTs_TAG }; _i.u.FSQRTs.fs2 = fs2; _i.u.FSQRTs.fd = fd; return _i; } /************** FSQRTd fs2, fd is (FSQRTd) op == 2 & op3 == 52 & opf == 42 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSQRTd(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSQRTd_TAG }; _i.u.FSQRTd.fs2 = fs2; _i.u.FSQRTd.fd = fd; return _i; } /************** FSQRTq fs2, fd is (FSQRTq) op == 2 & op3 == 52 & opf == 43 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSQRTq(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSQRTq_TAG }; _i.u.FSQRTq.fs2 = fs2; _i.u.FSQRTq.fd = fd; return _i; } /************** FiTOs fs2, fd is (FiTOs) op == 2 & op3 == 52 & opf == 196 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FiTOs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FiTOs_TAG }; _i.u.FiTOs.fs2 = fs2; _i.u.FiTOs.fd = fd; return _i; } /************** FsTOi fs2, fd is (FsTOi) op == 2 & op3 == 52 & opf == 209 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FsTOi(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FsTOi_TAG }; _i.u.FsTOi.fs2 = fs2; _i.u.FsTOi.fd = fd; return _i; } /************** FiTOd fs2, fd is (FiTOd) op == 2 & op3 == 52 & opf == 200 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FiTOd(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FiTOd_TAG }; _i.u.FiTOd.fs2 = fs2; _i.u.FiTOd.fd = fd; return _i; } /************** FsTOd fs2, fd is (FsTOd) op == 2 & op3 == 52 & opf == 201 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FsTOd(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FsTOd_TAG }; _i.u.FsTOd.fs2 = fs2; _i.u.FsTOd.fd = fd; return _i; } /************** FiTOq fs2, fd is (FiTOq) op == 2 & op3 == 52 & opf == 204 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FiTOq(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FiTOq_TAG }; _i.u.FiTOq.fs2 = fs2; _i.u.FiTOq.fd = fd; return _i; } /************** FsTOq fs2, fd is (FsTOq) op == 2 & op3 == 52 & opf == 205 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FsTOq(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FsTOq_TAG }; _i.u.FsTOq.fs2 = fs2; _i.u.FsTOq.fd = fd; return _i; } /************** FdTOi fs2, fd is (FdTOi) op == 2 & op3 == 52 & opf == 210 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FdTOi(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FdTOi_TAG }; _i.u.FdTOi.fs2 = fs2; _i.u.FdTOi.fd = fd; return _i; } /************** FdTOs fs2, fd is (FdTOs) op == 2 & op3 == 52 & opf == 198 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FdTOs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FdTOs_TAG }; _i.u.FdTOs.fs2 = fs2; _i.u.FdTOs.fd = fd; return _i; } /************** FqTOs fs2, fd is (FqTOs) op == 2 & op3 == 52 & opf == 199 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FqTOs(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FqTOs_TAG }; _i.u.FqTOs.fs2 = fs2; _i.u.FqTOs.fd = fd; return _i; } /************** FqTOi fs2, fd is (FqTOi) op == 2 & op3 == 52 & opf == 211 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FqTOi(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FqTOi_TAG }; _i.u.FqTOi.fs2 = fs2; _i.u.FqTOi.fd = fd; return _i; } /************** FqTOd fs2, fd is (FqTOd) op == 2 & op3 == 52 & opf == 203 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FqTOd(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FqTOd_TAG }; _i.u.FqTOd.fs2 = fs2; _i.u.FqTOd.fd = fd; return _i; } /************** FdTOq fs2, fd is (FdTOq) op == 2 & op3 == 52 & opf == 206 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FdTOq(unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FdTOq_TAG }; _i.u.FdTOq.fs2 = fs2; _i.u.FdTOq.fd = fd; return _i; } /************** FADDs fs1, fs2, fd is (FADDs) op == 2 & op3 == 52 & opf == 65 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FADDs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FADDs_TAG }; _i.u.FADDs.fs1 = fs1; _i.u.FADDs.fs2 = fs2; _i.u.FADDs.fd = fd; return _i; } /************** FSUBs fs1, fs2, fd is (FSUBs) op == 2 & op3 == 52 & opf == 69 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSUBs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSUBs_TAG }; _i.u.FSUBs.fs1 = fs1; _i.u.FSUBs.fs2 = fs2; _i.u.FSUBs.fd = fd; return _i; } /************** FMULs fs1, fs2, fd is (FMULs) op == 2 & op3 == 52 & opf == 73 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FMULs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FMULs_TAG }; _i.u.FMULs.fs1 = fs1; _i.u.FMULs.fs2 = fs2; _i.u.FMULs.fd = fd; return _i; } /************** FDIVs fs1, fs2, fd is (FDIVs) op == 2 & op3 == 52 & opf == 77 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FDIVs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FDIVs_TAG }; _i.u.FDIVs.fs1 = fs1; _i.u.FDIVs.fs2 = fs2; _i.u.FDIVs.fd = fd; return _i; } /************** FADDd fs1, fs2, fd is (FADDd) op == 2 & op3 == 52 & opf == 66 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FADDd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FADDd_TAG }; _i.u.FADDd.fs1 = fs1; _i.u.FADDd.fs2 = fs2; _i.u.FADDd.fd = fd; return _i; } /************** FSUBd fs1, fs2, fd is (FSUBd) op == 2 & op3 == 52 & opf == 70 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSUBd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSUBd_TAG }; _i.u.FSUBd.fs1 = fs1; _i.u.FSUBd.fs2 = fs2; _i.u.FSUBd.fd = fd; return _i; } /************** FMULd fs1, fs2, fd is (FMULd) op == 2 & op3 == 52 & opf == 74 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FMULd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FMULd_TAG }; _i.u.FMULd.fs1 = fs1; _i.u.FMULd.fs2 = fs2; _i.u.FMULd.fd = fd; return _i; } /************** FDIVd fs1, fs2, fd is (FDIVd) op == 2 & op3 == 52 & opf == 78 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FDIVd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FDIVd_TAG }; _i.u.FDIVd.fs1 = fs1; _i.u.FDIVd.fs2 = fs2; _i.u.FDIVd.fd = fd; return _i; } /************** FADDq fs1, fs2, fd is (FADDq) op == 2 & op3 == 52 & opf == 67 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FADDq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FADDq_TAG }; _i.u.FADDq.fs1 = fs1; _i.u.FADDq.fs2 = fs2; _i.u.FADDq.fd = fd; return _i; } /************** FSUBq fs1, fs2, fd is (FSUBq) op == 2 & op3 == 52 & opf == 71 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FSUBq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FSUBq_TAG }; _i.u.FSUBq.fs1 = fs1; _i.u.FSUBq.fs2 = fs2; _i.u.FSUBq.fd = fd; return _i; } /************** FMULq fs1, fs2, fd is (FMULq) op == 2 & op3 == 52 & opf == 75 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FMULq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FMULq_TAG }; _i.u.FMULq.fs1 = fs1; _i.u.FMULq.fs2 = fs2; _i.u.FMULq.fd = fd; return _i; } /************** FDIVq fs1, fs2, fd is (FDIVq) op == 2 & op3 == 52 & opf == 79 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FDIVq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FDIVq_TAG }; _i.u.FDIVq.fs1 = fs1; _i.u.FDIVq.fs2 = fs2; _i.u.FDIVq.fd = fd; return _i; } /************** FsMULd fs1, fs2, fd is (FsMULd) op == 2 & op3 == 52 & opf == 105 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FsMULd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FsMULd_TAG }; _i.u.FsMULd.fs1 = fs1; _i.u.FsMULd.fs2 = fs2; _i.u.FsMULd.fd = fd; return _i; } /************** FdMULq fs1, fs2, fd is (FdMULq) op == 2 & op3 == 52 & opf == 110 & fs1 = fs1 & fs2 = fs2 & fd = fd ***********/ static instruction_Instance FdMULq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2, unsigned /* [0..31] */ fd) { instruction_Instance _i = { FdMULq_TAG }; _i.u.FdMULq.fs1 = fs1; _i.u.FdMULq.fs2 = fs2; _i.u.FdMULq.fd = fd; return _i; } /************** FCMPs fs1, fs2 is (FCMPs) op == 2 & op3 == 53 & opf == 81 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPs_TAG }; _i.u.FCMPs.fs1 = fs1; _i.u.FCMPs.fs2 = fs2; return _i; } /************** FCMPEs fs1, fs2 is (FCMPEs) op == 2 & op3 == 53 & opf == 85 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPEs(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPEs_TAG }; _i.u.FCMPEs.fs1 = fs1; _i.u.FCMPEs.fs2 = fs2; return _i; } /************** FCMPd fs1, fs2 is (FCMPd) op == 2 & op3 == 53 & opf == 82 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPd_TAG }; _i.u.FCMPd.fs1 = fs1; _i.u.FCMPd.fs2 = fs2; return _i; } /************** FCMPEd fs1, fs2 is (FCMPEd) op == 2 & op3 == 53 & opf == 86 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPEd(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPEd_TAG }; _i.u.FCMPEd.fs1 = fs1; _i.u.FCMPEd.fs2 = fs2; return _i; } /************** FCMPq fs1, fs2 is (FCMPq) op == 2 & op3 == 53 & opf == 83 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPq_TAG }; _i.u.FCMPq.fs1 = fs1; _i.u.FCMPq.fs2 = fs2; return _i; } /************** FCMPEq fs1, fs2 is (FCMPEq) op == 2 & op3 == 53 & opf == 87 & fs1 = fs1 & fs2 = fs2 ***********/ static instruction_Instance FCMPEq(unsigned /* [0..31] */ fs1, unsigned /* [0..31] */ fs2) { instruction_Instance _i = { FCMPEq_TAG }; _i.u.FCMPEq.fs1 = fs1; _i.u.FCMPEq.fs2 = fs2; return _i; } /************** NOP is (NOP) op == 0 & op2 == 4 & rd == 0 & imm22 == 0 ***********/ static instruction_Instance NOP(void) { instruction_Instance _i = { NOP_TAG }; return _i; } /************** FLUSH address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 59 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 59 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 59 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 59 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 59 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 59 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance FLUSH(address__Instance address_) { instruction_Instance _i = { FLUSH_TAG }; _i.u.FLUSH.address_ = address_; return _i; } /************** JMPL address_, rd is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = rd | dispA => (?noname?) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = rd | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = rd | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = rd END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = rd | indirectA => (?noname?) (?address_:): op == 2 & op3 == 56 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = rd END (* address_ *) ***********/ static instruction_Instance JMPL(address__Instance address_, unsigned /* [0..31] */ rd) { instruction_Instance _i = { JMPL_TAG }; _i.u.JMPL.address_ = address_; _i.u.JMPL.rd = rd; return _i; } /************** RETT address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 57 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 57 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 57 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 57 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 57 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 57 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance RETT(address__Instance address_) { instruction_Instance _i = { RETT_TAG }; _i.u.RETT.address_ = address_; return _i; } /************** TN address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 0 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 0 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 0 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 0 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 0 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 0 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TN(address__Instance address_) { instruction_Instance _i = { TN_TAG }; _i.u.TN.address_ = address_; return _i; } /************** TE address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 1 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 1 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 1 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 1 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 1 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 1 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TE(address__Instance address_) { instruction_Instance _i = { TE_TAG }; _i.u.TE.address_ = address_; return _i; } /************** TLE address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 2 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 2 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 2 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 2 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 2 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 2 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TLE(address__Instance address_) { instruction_Instance _i = { TLE_TAG }; _i.u.TLE.address_ = address_; return _i; } /************** TL address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 3 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 3 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 3 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 3 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 3 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 3 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TL(address__Instance address_) { instruction_Instance _i = { TL_TAG }; _i.u.TL.address_ = address_; return _i; } /************** TLEU address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 4 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 4 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 4 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 4 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 4 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 4 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TLEU(address__Instance address_) { instruction_Instance _i = { TLEU_TAG }; _i.u.TLEU.address_ = address_; return _i; } /************** TCS address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 5 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 5 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 5 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 5 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 5 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 5 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TCS(address__Instance address_) { instruction_Instance _i = { TCS_TAG }; _i.u.TCS.address_ = address_; return _i; } /************** TNEG address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 6 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 6 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 6 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 6 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 6 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 6 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TNEG(address__Instance address_) { instruction_Instance _i = { TNEG_TAG }; _i.u.TNEG.address_ = address_; return _i; } /************** TVS address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 7 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 7 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 7 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 7 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 7 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 7 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TVS(address__Instance address_) { instruction_Instance _i = { TVS_TAG }; _i.u.TVS.address_ = address_; return _i; } /************** TA address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 8 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 8 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 8 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 8 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 8 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 8 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TA(address__Instance address_) { instruction_Instance _i = { TA_TAG }; _i.u.TA.address_ = address_; return _i; } /************** TNE address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 9 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 9 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 9 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 9 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 9 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 9 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TNE(address__Instance address_) { instruction_Instance _i = { TNE_TAG }; _i.u.TNE.address_ = address_; return _i; } /************** TG address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 10 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 10 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 10 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 10 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 10 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 10 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TG(address__Instance address_) { instruction_Instance _i = { TG_TAG }; _i.u.TG.address_ = address_; return _i; } /************** TGE address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 11 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 11 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 11 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 11 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 11 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 11 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TGE(address__Instance address_) { instruction_Instance _i = { TGE_TAG }; _i.u.TGE.address_ = address_; return _i; } /************** TGU address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 12 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 12 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 12 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 12 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 12 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 12 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TGU(address__Instance address_) { instruction_Instance _i = { TGU_TAG }; _i.u.TGU.address_ = address_; return _i; } /************** TCC address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 13 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 13 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 13 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 13 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 13 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 13 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TCC(address__Instance address_) { instruction_Instance _i = { TCC_TAG }; _i.u.TCC.address_ = address_; return _i; } /************** TPOS address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 14 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 14 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 14 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 14 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 14 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 14 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TPOS(address__Instance address_) { instruction_Instance _i = { TPOS_TAG }; _i.u.TPOS.address_ = address_; return _i; } /************** TVC address_ is CASE address_ OF | absoluteA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 15 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 | dispA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 15 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 15 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 | rmode => (?noname?) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 58 & cond == 15 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 END (* address_.generalA.reg_or_imm *) | indexA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 15 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 | indirectA => (?noname?) (?address_:): op == 2 & op3 == 58 & cond == 15 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 END (* address_ *) ***********/ static instruction_Instance TVC(address__Instance address_) { instruction_Instance _i = { TVC_TAG }; _i.u.TVC.address_ = address_; return _i; } /************** UNIMP imm22 is (UNIMP) op == 0 & op2 == 0 & imm22 = imm22 ***********/ static instruction_Instance UNIMP(unsigned /* [0..4194303] */ imm22) { instruction_Instance _i = { UNIMP_TAG }; if (!((unsigned)(imm22) < 0x400000)) (*fail) ("imm22 = %d won't fit in 22 unsigned bits"); _i.u.UNIMP.imm22 = imm22; return _i; } /************** sethi %hi(val), rd is (SETHI) op == 0 & op2 == 4 & rd = rd & imm22 = val[10:31] ***********/ static instruction_Instance sethi(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { sethi_TAG }; _i.u.sethi.val = val; _i.u.sethi.rd = rd; return _i; } /************** decode_sethi %hi(val), rd is (SETHI) {val[0:9] = 0} => op == 0 & op2 == 4 & rd = rd & imm22 = val[10:31] ***********/ static instruction_Instance decode_sethi(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { decode_sethi_TAG }; _i.u.decode_sethi.val = val; _i.u.decode_sethi.rd = rd; return _i; } /************** cmp rs1, reg_or_imm is CASE reg_or_imm OF | imode => (SUBcc) (?reg_or_imm:): op == 2 & op3 == 20 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = 0 | rmode => (SUBcc) (?reg_or_imm:): op == 2 & op3 == 20 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = 0 END (* reg_or_imm *) ***********/ static instruction_Instance cmp(unsigned /* [0..31] */ rs1, reg_or_imm_Instance reg_or_imm) { instruction_Instance _i = { cmp_TAG }; _i.u.cmp.rs1 = rs1; _i.u.cmp.reg_or_imm = reg_or_imm; return _i; } /************** jmp address_ is CASE address_ OF | absoluteA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = 0 | dispA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = 0 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (JMPL) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = 0 | rmode => (JMPL) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = 0 END (* address_.generalA.reg_or_imm *) | indexA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = 0 | indirectA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = 0 END (* address_ *) ***********/ static instruction_Instance jmp(address__Instance address_) { instruction_Instance _i = { jmp_TAG }; _i.u.jmp.address_ = address_; return _i; } /************** calla address_ is CASE address_ OF | absoluteA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = 15 | dispA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = 15 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (JMPL) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = 15 | rmode => (JMPL) (?address_:): (?address_.generalA.reg_or_imm:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = 15 END (* address_.generalA.reg_or_imm *) | indexA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = 15 | indirectA => (JMPL) (?address_:): op == 2 & op3 == 56 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = 15 END (* address_ *) ***********/ static instruction_Instance calla(address__Instance address_) { instruction_Instance _i = { calla_TAG }; _i.u.calla.address_ = address_; return _i; } /************** tst rs2 is (ORcc) op == 2 & op3 == 18 & i == 0 & rs2 = rs2 & rs1 = 0 & rd = 0 ***********/ static instruction_Instance tst(unsigned /* [0..31] */ rs2) { instruction_Instance _i = { tst_TAG }; _i.u.tst.rs2 = rs2; return _i; } /************** ret is (JMPL) op == 2 & op3 == 56 & i == 1 & rs1 = 31 & simm13 = 8 & rd = 0 ***********/ static instruction_Instance ret(void) { instruction_Instance _i = { ret_TAG }; return _i; } /************** retl is (JMPL) op == 2 & op3 == 56 & i == 1 & rs1 = 15 & simm13 = 8 & rd = 0 ***********/ static instruction_Instance retl(void) { instruction_Instance _i = { retl_TAG }; return _i; } /************** restore_ is (RESTORE) op == 2 & op3 == 61 & i == 0 & rs2 = 0 & rs1 = 0 & rd = 0 ***********/ static instruction_Instance restore_(void) { instruction_Instance _i = { restore__TAG }; return _i; } /************** save_ is (SAVE) op == 2 & op3 == 60 & i == 0 & rs2 = 0 & rs1 = 0 & rd = 0 ***********/ static instruction_Instance save_(void) { instruction_Instance _i = { save__TAG }; return _i; } /************** not rd is (XNOR) op == 2 & op3 == 7 & i == 0 & rs2 = 0 & rs1 = rd & rd = rd ***********/ static instruction_Instance not(unsigned /* [0..31] */ rd) { instruction_Instance _i = { not_TAG }; _i.u.not.rd = rd; return _i; } /************** not2 rs1, rd is (XNOR) op == 2 & op3 == 7 & i == 0 & rs2 = 0 & rs1 = rs1 & rd = rd ***********/ static instruction_Instance not2(unsigned /* [0..31] */ rs1, unsigned /* [0..31] */ rd) { instruction_Instance _i = { not2_TAG }; _i.u.not2.rs1 = rs1; _i.u.not2.rd = rd; return _i; } /************** neg rd is (SUB) op == 2 & op3 == 4 & i == 0 & rs2 = rd & rs1 = 0 & rd = rd ***********/ static instruction_Instance neg(unsigned /* [0..31] */ rd) { instruction_Instance _i = { neg_TAG }; _i.u.neg.rd = rd; return _i; } /************** neg2 rs2, rd is (SUB) op == 2 & op3 == 4 & i == 0 & rs2 = rs2 & rs1 = 0 & rd = rd ***********/ static instruction_Instance neg2(unsigned /* [0..31] */ rs2, unsigned /* [0..31] */ rd) { instruction_Instance _i = { neg2_TAG }; _i.u.neg2.rs2 = rs2; _i.u.neg2.rd = rd; return _i; } /************** inc val, rd is (ADD) op == 2 & op3 == 0 & i == 1 & simm13 = val[13!] & rs1 = rd & rd = rd ***********/ static instruction_Instance inc(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { inc_TAG }; _i.u.inc.val = val; _i.u.inc.rd = rd; return _i; } /************** inccc val, rd is (ADDcc) op == 2 & op3 == 16 & i == 1 & simm13 = val[13!] & rs1 = rd & rd = rd ***********/ static instruction_Instance inccc(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { inccc_TAG }; _i.u.inccc.val = val; _i.u.inccc.rd = rd; return _i; } /************** dec val, rd is (SUB) op == 2 & op3 == 4 & i == 1 & simm13 = val[13!] & rs1 = rd & rd = rd ***********/ static instruction_Instance dec(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { dec_TAG }; _i.u.dec.val = val; _i.u.dec.rd = rd; return _i; } /************** deccc val, rd is (SUBcc) op == 2 & op3 == 20 & i == 1 & simm13 = val[13!] & rs1 = rd & rd = rd ***********/ static instruction_Instance deccc(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { deccc_TAG }; _i.u.deccc.val = val; _i.u.deccc.rd = rd; return _i; } /************** btst reg_or_imm, rs1 is CASE reg_or_imm OF | imode => (ANDcc) (?reg_or_imm:): op == 2 & op3 == 17 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rs1 & rd = 0 | rmode => (ANDcc) (?reg_or_imm:): op == 2 & op3 == 17 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rs1 & rd = 0 END (* reg_or_imm *) ***********/ static instruction_Instance btst(reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rs1) { instruction_Instance _i = { btst_TAG }; _i.u.btst.reg_or_imm = reg_or_imm; _i.u.btst.rs1 = rs1; return _i; } /************** bset reg_or_imm, rd is CASE reg_or_imm OF | imode => (OR) (?reg_or_imm:): op == 2 & op3 == 2 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rd & rd = rd | rmode => (OR) (?reg_or_imm:): op == 2 & op3 == 2 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rd & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance bset(reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { bset_TAG }; _i.u.bset.reg_or_imm = reg_or_imm; _i.u.bset.rd = rd; return _i; } /************** bclr reg_or_imm, rd is CASE reg_or_imm OF | imode => (ANDN) (?reg_or_imm:): op == 2 & op3 == 5 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rd & rd = rd | rmode => (ANDN) (?reg_or_imm:): op == 2 & op3 == 5 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rd & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance bclr(reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { bclr_TAG }; _i.u.bclr.reg_or_imm = reg_or_imm; _i.u.bclr.rd = rd; return _i; } /************** btog reg_or_imm, rd is CASE reg_or_imm OF | imode => (XOR) (?reg_or_imm:): op == 2 & op3 == 3 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = rd & rd = rd | rmode => (XOR) (?reg_or_imm:): op == 2 & op3 == 3 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = rd & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance btog(reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { btog_TAG }; _i.u.btog.reg_or_imm = reg_or_imm; _i.u.btog.rd = rd; return _i; } /************** clr rd is (OR) op == 2 & op3 == 2 & i == 0 & rs2 = 0 & rs1 = 0 & rd = rd ***********/ static instruction_Instance clr(unsigned /* [0..31] */ rd) { instruction_Instance _i = { clr_TAG }; _i.u.clr.rd = rd; return _i; } /************** clrw [address_] is CASE address_ OF | absoluteA => (ST) (?address_:): op == 3 & op3 == 4 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = 0 | dispA => (ST) (?address_:): op == 3 & op3 == 4 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = 0 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (ST) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 4 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = 0 | rmode => (ST) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 4 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = 0 END (* address_.generalA.reg_or_imm *) | indexA => (ST) (?address_:): op == 3 & op3 == 4 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = 0 | indirectA => (ST) (?address_:): op == 3 & op3 == 4 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = 0 END (* address_ *) ***********/ static instruction_Instance clrw(address__Instance address_) { instruction_Instance _i = { clrw_TAG }; _i.u.clrw.address_ = address_; return _i; } /************** clrb [address_] is CASE address_ OF | absoluteA => (STB) (?address_:): op == 3 & op3 == 5 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = 0 | dispA => (STB) (?address_:): op == 3 & op3 == 5 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = 0 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (STB) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 5 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = 0 | rmode => (STB) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 5 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = 0 END (* address_.generalA.reg_or_imm *) | indexA => (STB) (?address_:): op == 3 & op3 == 5 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = 0 | indirectA => (STB) (?address_:): op == 3 & op3 == 5 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = 0 END (* address_ *) ***********/ static instruction_Instance clrb(address__Instance address_) { instruction_Instance _i = { clrb_TAG }; _i.u.clrb.address_ = address_; return _i; } /************** clrh [address_] is CASE address_ OF | absoluteA => (STH) (?address_:): op == 3 & op3 == 6 & i == 1 & rs1 = 0 & simm13 = address_.absoluteA.simm13 & rd = 0 | dispA => (STH) (?address_:): op == 3 & op3 == 6 & i == 1 & rs1 = address_.dispA.rs1 & simm13 = address_.dispA.simm13 & rd = 0 | generalA => CASE address_.generalA.reg_or_imm OF | imode => (STH) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 6 & i == 1 & rs1 = address_.generalA.rs1 & simm13 = address_.generalA.reg_or_imm.imode.simm13 & rd = 0 | rmode => (STH) (?address_:): (?address_.generalA.reg_or_imm:): op == 3 & op3 == 6 & i == 0 & rs1 = address_.generalA.rs1 & rs2 = address_.generalA.reg_or_imm.rmode.rs2 & rd = 0 END (* address_.generalA.reg_or_imm *) | indexA => (STH) (?address_:): op == 3 & op3 == 6 & i == 0 & rs1 = address_.indexA.rs1 & rs2 = address_.indexA.rs2 & rd = 0 | indirectA => (STH) (?address_:): op == 3 & op3 == 6 & i == 0 & rs2 = 0 & rs1 = address_.indirectA.rs1 & rd = 0 END (* address_ *) ***********/ static instruction_Instance clrh(address__Instance address_) { instruction_Instance _i = { clrh_TAG }; _i.u.clrh.address_ = address_; return _i; } /************** mov reg_or_imm, rd is CASE reg_or_imm OF | imode => (OR) (?reg_or_imm:): op == 2 & op3 == 2 & i == 1 & simm13 = reg_or_imm.imode.simm13 & rs1 = 0 & rd = rd | rmode => (OR) (?reg_or_imm:): op == 2 & op3 == 2 & i == 0 & rs2 = reg_or_imm.rmode.rs2 & rs1 = 0 & rd = rd END (* reg_or_imm *) ***********/ static instruction_Instance mov(reg_or_imm_Instance reg_or_imm, unsigned /* [0..31] */ rd) { instruction_Instance _i = { mov_TAG }; _i.u.mov.reg_or_imm = reg_or_imm; _i.u.mov.rd = rd; return _i; } /************** movr rs2, rd is (OR) op == 2 & op3 == 2 & i == 0 & rs2 = rs2 & rs1 = 0 & rd = rd ***********/ static instruction_Instance movr(unsigned /* [0..31] */ rs2, unsigned /* [0..31] */ rd) { instruction_Instance _i = { movr_TAG }; _i.u.movr.rs2 = rs2; _i.u.movr.rd = rd; return _i; } /************** set val, rd is (SETHI) {val[0:9] = 0} => op == 0 & op2 == 4 & rd = rd & imm22 = val[10:31] | (OR) op == 2 & op3 == 2 & i == 1 & simm13 = val[13!] & rs1 = 0 & rd = rd | (?noname?) op == 0 & op2 == 4 & rd = rd & imm22 = val[10:31]; op == 2 & op3 == 2 & i == 1 & simm13 = val[0:9][13!] & rs1 = rd & rd = rd ***********/ static instruction_Instance set(int val, unsigned /* [0..31] */ rd) { instruction_Instance _i = { set_TAG }; _i.u.set.val = val; _i.u.set.rd = rd; return _i; } static struct sparc encoding_procs = {imode, rmode, generalA, dispA, absoluteA, indexA, indirectA, LDSB, LDSH, LDUB, LDUH, LD, LDSTUB, SWAP_, LDD, LDF, LDDF, LDC, LDDC, STB, STH, ST, STD, STF, STDF, STC, STDC, indexR, indirectR, LDSBA, LDSHA, LDUBA, LDUHA, LDA, LDSTUBA, SWAPA, LDDA, STBA, STHA, STA, STDA, LDFSR, LDCSR, STFSR, STCSR, STDFQ, STDCQ, RDY, RDPSR, RDWIM, RDTBR, WRY, WRPSR, WRWIM, WRTBR, RDASR, WRASR, STBAR, AND, ANDcc, ANDN, ANDNcc, OR, ORcc, ORN, ORNcc, XOR, XORcc, XNOR, XNORcc, SLL, SRL, SRA, ADD, ADDcc, ADDX, ADDXcc, TADDcc, TADDccTV, SUB, SUBcc, SUBX, SUBXcc, TSUBcc, TSUBccTV, MULScc, UMUL, SMUL, UMULcc, SMULcc, UDIV, SDIV, UDIVcc, SDIVcc, SAVE, RESTORE, BN, BN_a, BE, BE_a, BLE, BLE_a, BL, BL_a, BLEU, BLEU_a, BCS, BCS_a, BNEG, BNEG_a, BVS, BVS_a, BA, BA_a, BNE, BNE_a, BG, BG_a, BGE, BGE_a, BGU, BGU_a, BCC, BCC_a, BPOS, BPOS_a, BVC, BVC_a, FBN, FBN_a, FBNE, FBNE_a, FBLG, FBLG_a, FBUL, FBUL_a, FBL, FBL_a, FBUG, FBUG_a, FBG, FBG_a, FBU, FBU_a, FBA, FBA_a, FBE, FBE_a, FBUE, FBUE_a, FBGE, FBGE_a, FBUGE, FBUGE_a, FBLE, FBLE_a, FBULE, FBULE_a, FBO, FBO_a, CBN, CBN_a, CB123, CB123_a, CB12, CB12_a, CB13, CB13_a, CB1, CB1_a, CB23, CB23_a, CB2, CB2_a, CB3, CB3_a, CBA, CBA_a, CB0, CB0_a, CB03, CB03_a, CB02, CB02_a, CB023, CB023_a, CB01, CB01_a, CB013, CB013_a, CB012, CB012_a, call, FMOVs, FNEGs, FABSs, FSQRTs, FSQRTd, FSQRTq, FiTOs, FsTOi, FiTOd, FsTOd, FiTOq, FsTOq, FdTOi, FdTOs, FqTOs, FqTOi, FqTOd, FdTOq, FADDs, FSUBs, FMULs, FDIVs, FADDd, FSUBd, FMULd, FDIVd, FADDq, FSUBq, FMULq, FDIVq, FsMULd, FdMULq, FCMPs, FCMPEs, FCMPd, FCMPEd, FCMPq, FCMPEq, NOP, FLUSH, JMPL, RETT, TN, TE, TLE, TL, TLEU, TCS, TNEG, TVS, TA, TNE, TG, TGE, TGU, TCC, TPOS, TVC, UNIMP, sethi, decode_sethi, cmp, jmp, calla, tst, ret, retl, restore_, save_, not, not2, neg, neg2, inc, inccc, dec, deccc, btst, bset, bclr, btog, clr, clrw, clrb, clrh, mov, movr, set, }; struct sparc *sparc = &encoding_procs; ClosurePostfix sparc_enc_clofuns[] = { { (ApplyMethod) 0, (char *) 0 } }; ClosurePostfix sparc_enc_clobytes[] = { { (ApplyMethod) 0, (char *) 0 } }; /* Bytecode total is 0 */