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Design Automation Summer School
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To download the tar.gz file for all problems and solutions, click here.
You will also need the GTL library and the systemC libraries - Check out platform information.
Problem 1: Analysis & Circuit Design
Submitted by Frank Liu, IBM Research Labs in Austin
Overview: Estimating delays of on-chip interconnect plays a major role in
the design and verification of digital circuits. The students should
focus on understanding how the CRC pi-segment model approximation
(equations 14-16 in the reference paper) can be computed for a given
generalized RC tree.
"Modeling the Driving-Point Characteristic of Resistive Interconnect
for Accurate Delay Estimation," Peter R. O'Brien & Thomas L. Savarino,
ICCAD, 1989, pp. 512-515.
Problem 2: Physical Design
Submitted by Patrick Madden, Binghamton, NY
Overview:
The paper below gives an overview of a popular placement algorithm. Students should become familiar with the optimization objectives and also the techniques outlined in this paper.
"Algorithms for Large-Scale Placement,"
Jens Vygen, DAC, 1997.
Problem 3: Logic & High-Level Synthesis
Submitted by Geert Janssen, IBM, Watson
Overview:
Although the DAGON paper is rather classical, its principles are still
in use today. The CADathlon related problem will focus on structural
technology mapping of a normalized (or canonical) circuit to a
prescribed library of cells. The solution should be optimal with
respect to a certain cost function.
"DAGON: Technology Binding and Local Optimization in DAG Matching,"
Kurt Keutzer, Design Automation Conference, 1987, pp. 341-347
Problem 4: System Design and Analysis
Submitted by Sandeep Shukla, Virginia Tech
Overview:
Most real-time models operate concurrently. These models can be
implemented in SystemC as clocked threads. Simulation efficiency of
the SystemC model generally decreases with increase in the number of
threads. Thus, as the complexity of the models increase, simulation
efficiency might be poor.
To solve the relevant CADathlon problem, the student should gain some
knowledge of the structure of a SystemC program and understand how to
use sc_methods in SystemC. A good introductory SystemC example is in
Chapter 2 in the SystemC Version 2.0.1 Users guide available on the
www.systemc.org web site. Furthermore, the students should focus on
*broadly* understanding the concurrency re-assignment strategy
outlined in the paper, and on learning how to use SystemC threads.
"Automated Concurrency Re-assignment in High Level System Models
for Efficient System-Level Simulation,"
Nick Savoiu, Sandeep Shukla, Rajesh Gupta, DATE, 2002
SystemC Users Guide
http://www.systemc.org/projects/sitedocs/document/v201_Users_guide/en/1
Problem 5: Functional Verification
Submitted by Geert Janssen, IBM, Watson
Overview:
Sequential circuit verification is a broad area of research.
Make sure that you understand the theory behind reachability analysis
and the algorithms involved. Also consider how to apply BDDs in this
context.
"A Unified Framework for the Formal Verification of Sequential Circuits,"
Olivier Coudert, Jean Christophe Madre,
ICCAD, 1990, Santa Clara, CA, pp. 126-129
Problem 6: Timing, Test, and Manufacturing
Submitted by Soha Hassoun, Tufts University
Overview:
The reference paper deals with clock schedule verification for
circuits that contain level-sensitive latches. The related CADathlon
problem requires students to understand the SMO clocking model, the
relationship between arrival and departure times while considering the
phase shift operations, and the underlying circuit graph model. Also,
consider how the proposed algorithm will be simplified if no physical
loops exist within the circuit graph.
"Verifying Clock Schedules,"
Thomas G. Szymanski, Narendra Shenoy,
ICCAD 1992, pp. 124-131
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