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CADathlon 2002
SIGDA Sister Forums
Ph.D. Forum at DAC
Design Automation Summer School
Sponsored by SIGDA
with contributions from IBM & Intel
SIGDA Contact
Dr. Soha Hassoun
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To download the tar.gz file for all related papers, click here.
To download the setup and solutions for all problems, click
here.
Problem 1: Analysis & Circuit Design
Overview:
In this problem you will calculate the supply voltage drop
at selected locations on the power grid. The related paper
will provide the basis.
"Random Walks in a Supply Network",
H. Qian, S.R. Nassif and S.S. Sapatnekar
Proceedings of ACM/IEEE Design Automation Conference
pp. 93-98, June 2003
Problem 2: Physical Design
Overview: Buffer insertion is crucial for optimal routing.
The problem here concerns programming a method to
place buffers in a fanout tree network to decrease the
Elmore delay of the signal.
"Buffer Placement in Distributed RC-tree Networks for Minimal Elmore Delay",
Lukas P.P.P. van Ginneken,
Proceedings IEEE International Symposium on Circuits and Systems,
Vol. 2, pp. 865-868, May 1-3, 1990
Problem 3: Logic & High-Level Synthesis
Overview:
Retiming, first introduced by Leiserson, Saxe, and Rose, has been applied
to optimize sequential low and high-level designs. The related CADathlon
problem will be concerned with retiming to minimize the clock period (up to section 6 in the
reference paper).
"Retiming Synchronous Circuitry",
Charles E. Leiserson, James B. Saxe, Digital Systems Research Center, Report 18,
August 20, 1986.
Problem 4: System Design and Analysis
Overview:
The paper below gives several examples of how ILP can be used to solve
a scheduling problem. Make sure you gain familiarity with the algorithms
described therein and understand how to derive the constraints for the
ILP solver from a design.
"A Formal Approach to the Scheduling Problem in High Level Synthesis",
Cheng-Tsung Hwang, Jiahn-Hurng Lee, and Yu-Chin Hsu,
IEEE Transactions on Computer-Aided Design, Vol. 10, No. 4, April 1991
Problem 5: Functional Verification
Overview:
The programming task comprises the use of a SAT solver to verify
combinational circuits.
"Faster SAT and Smaller BDDs via Common Function Structure",
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah,
University Michigan, Technical Report,
December 12, 2001
Problem 6: Timing, Test, and Manufacturing
Overview:
Fault simulation is used extensively at the core of several algorithms
in VLSI test. The contestants are expected to understand the basic
concepts and performance issues related to different algorithms for
fault simulation described in the reference below (all in postscript).
Excerpt from Essentials of Electronic Testing for Digital, Memory,
and Mixed-Signal VLSI Circuits, Michael L. Bushnell and
Vishwani D. Agrawal, Kluwer Academic Publishers, 2000.
The references, if needed, for these pages are here.
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