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CADathlon 03 @ ICCAD ParticipantsTeam: CADastrophicTeam Member: Abhijit DavareAdvisor: Alberto Sangiovanni-Vincentelli University: University of California, Berkeley Abhijit Davare is a doctoral student in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He received a B.S. degree in Computer Engineering from the University of Pittsburgh in 2002. He is interested in embedded systems design, low-power design, and sensor networks. Abhijit's current research involves design space exploration within the Metropolis project.Team Member: Douglas Densmore Advisor: Alberto Sangiovanni-Vincentelli University: University of California, Berkeley Doug Densmore is an Electrical Engineering PhD student at the University of California, Berkeley working under Prof. Alberto Sangiovanni-Vincentelli. He graduated in 2001 from the University of Michigan with a BSE in Computer Engineering. His academic interests include system-level design, reconfigurable logic, and formal verification. He is currently working on the Metropolis project at Berkeley in the area of Formal Refinement Verification.Official Team Number: 11 Team: Dr. SOCTeam Member: Youngchul ChoAdvisor: Kiyoung Choi University: Seoul National University I'm a third year Ph. D. student at Seoul National University. I've continued to study the stuffs on Electrical Engineering and Computer Science after 1996 without a stop. I have some experiences of the design of embedded system and the development of CAD through the projects collaborated by university and industries like Samsung.Team Member: Jun-hee Yoo Advisor: Kiyoung Choi University: Seoul National University 1. MS studentOfficial Team Number: 9 Team: CaipirinhaTeam Member: Renato Fernandes HentschkeAdvisor: Ricardo Reis University: UFRGS Renato is a PhD student at UFRGS working with physical design algorithms for routability. He achieved his master degree in computer science at UFRGS in 2002. His research interests are physical design, placement, congestion driven placement, routing and high level design space exploration.Team Member: Cristiano Lazzari Advisor: Ricardo Reis University: UFRGS Cristiano recently started PhD at UFRGS working with automatic layout generation for fault tolerant circuits. In the masters, Cristiano worked with automatic layout generation for digital circuits. His research interests are physical design, fault tolerance, radiation effects in VLSI circuits and satisfiability algorithms.Official Team Number: 18 Team: CubsTeam Member: Hosung(Leo) KimAdvisor: John Lillis University: University of Illinois at Chicago Hosung(Leo) Kim is currently a doctoral candidate in computer science at the university of Illinois at Chicago. His interests include design automation for VLSI, particularly logic synthesis and timing optimization.Team Member: Qingzhou(Ben) Wang Advisor: John Lillis University: University of Illinois at Chicago Ben is currently a Ph.D. student in computer science at the university of Illinois at Chicago. His interests include design automation for VLSI, Algorithms, particularly physical design (placement, timing optimization, etc.).Official Team Number: 10 Team: CMU_CADTeam Member: Jiayong LeAdvisor: Larry Pileggi University: Carnegie Mellon Jiayong Le is a graduate student in the ECE department at Carnegie Mellon, advised by Prof. Larry Pileggi. He received his BS and MS degree in Electrical Engineering in May 1999 and December 2001 from Shanghai Jiaotong University, China. His research interests are in circuit simulation and statistical timing analysis.Team Member: Veerbhan Kheterpal Advisor: Larry Pileggi University: Carnegie Mellon Veerbhan is a graduate student in the ECE department at Carnegie Mellon, advised by Prof. Larry Pileggi. He received his B.Tech. in Electronics & Electrical Communication Engineering in May 2002 from the Indian Institute of Technology, Kharagpur. His research interests are in logic synthesis, physical synthesis techniques, particularly focusing on applications to regular fabrics.Official Team Number: 15 Team: The also-ransTeam Member: Mahim MishraAdvisor: Seth C. Goldstein University: Carnegie Mellon University Mahim is a 3rd year graduate student in the Computer Science Department at Carnegie Mellon. His research interests include novel test methodologies, CAD tools and architectures for very large reconfigurable fabrics. Earlier, he received a B.Tech. degree in Computer Science and Engineering from the Indian Institute of Technology, Kanpur.Team Member: Saurabh Kumar Tiwary Advisor: Rob Rutenbar University: Carnegie Mellon University Saurabh received his B.Tech. degree in Electrical Engineering from IIT Kanpur (India). He is presently pursuing PhD in Electrical and Computer Engineering at Carnegie Mellon University. His interests include circuit macromodeling and analog CAD.Official Team Number: 19 Team: We don't rank treesTeam Member: Fei SunAdvisor: Niraj K. Jha University: Princeton University Fei Sun received the B.S. degree in Computer Science from Peking University, Beijing, China in 2000 and the M.A. degree in Electrical Engineering in 2002 from Princeton University, Princeton, NJ, USA, where he is currently pursuing the Ph.D. degree in Electrical Engineering.Team Member: Pallav Gupta Advisor: Niraj K. Jha University: Princeton University Pallav Gupta received his BS with Honors (summa cum laude) in computer engineering from The University of Arizona in 2001. He is presently a PhD student at Princeton University.Official Team Number: 4 Team: Wumpus HuntersTeam Member: Donald ChaiAdvisor: Andreas Kuehlmann University: UC Berkeley Donald Chai received his BS in Electrical Engineering and Computer Science at Cornell University in 2001. His research involves new techniques for fundamental CAD algorithms and synthesis techniques for low power.Team Member: Nathan Kitchen Advisor: Andreas Kuehlmann University: UC Berkeley Nathan Kitchen received his BS in Computer Engineering at Brigham Young University in 2002. Currently, his research focuses on sequential optimization and low-power synthesis.Official Team Number: 12 Team: University of ArizonaTeam Member: Sarvesh BhardwajAdvisor: Sarma Vrudhula University: Univeristy of Arizona Sarvesh Bhardwaj is a PhD student in the ECE Deptt of the University of Arizona, Tucson. He received his B. Tech. in EE from Indian Institute of Technology, Delhi in 2000 and M.S. in ECE from the University of Arizona in 2003. He has held VLSI Design Engineer positions in MindTree Technologies and Aplion Networks. He was a graduate intern at SUN Microsystems in summer 2003.Team Member: Kaviraj Chopra Advisor: Sarma Vrudhula University: University of Arizona Kaviraj Chopra received his Bachelor of Engineering in Instrumentation and Control from Gujarat University Government Engineering College Gandhinagar, India in 2001. He is currently working towards his Masters degree in Electrical and Computer engineering at the University of Arizona.Official Team Number: 14 Team: DAGgersTeam Member: Saurabh AdyaAdvisor: Prof. Igor Markov University: University of Michigan, Ann Arbor Saurabh Adya received his bachelor's degree in Electronics and Communication Engineering from KREC, Mangalore University, India in 1999 and a master's degree in Computer Science and Engineering from the University of Michigan, Ann Arbor, in 2002. He is currently a Ph.D candidate in the EECS department at the University of Michigan. From 1999 to 2000, he worked as IC Design Engineer at Texas Instruments, India. His current research interests are in the general area of VLSI CAD and specifically, physical design for VLSI.Team Member: Jarrod Roy Advisor: Prof. Igor Markov University: University of Michigan, Ann Arbor Jarrod Roy is a Ph.D pre-candidate at the University of Michigan. His areas of interest include physical design, SAT and QBF solving, and complexity theory. He received his B.S. in Computer Science (with university honors) from Carnegie Mellon University in May 2001 with an additional major in mathematics. University: Official Team Number: 5 Team: OrangemenTeam Member: Sachin SubhedarAdvisor: Roger Chen University: Syracuse University Sachin Subhedar is a PhD student in Computer Engineering at Syracuse University. He completed his undergraduate in Computer Science in 2000 and worked as a software engineer at Poseidon Technologies, Banglore, India. Professional experience included compiler design for retargetable embedded systems and ASIC architectural exploration. At masters level, he has worked on CAD logic design and formal verification projects. Currently he is involved in development of a synthesis tool for asynchronous circuits with timing constraints. Areas of research also include parallel programming and compilers for ASIC.Team Member: Chirag U.Sheth Advisor: Nazanin Mansouri University: Syracuse University Chirag Sheth is a Computer Engineering graduate student at Syracuse University. He will be graduating in December 2003. He completed his BS in Electronics from Bombay University. He has worked on development of several CAD tools for automation in VLSI designs. These include tools for logic design, physical design (layout generation of static CMOS complex gates), testing, floor planning and placement. He possesses strong analytical & problem solving skills. In addition, he also possesses strong interpersonal & leadership skills.Official Team Number: 1 Team: UIChampsTeam Member: Milos HrkicAdvisor: John Lillis University: University of Illinois at Chicago Milos Hrkic received the B.S. degree in computer science from the University of Illinois at Chicago. He is currently pursuing the Ph.D. degree in computer science at the University of Illinois at Chicago. His interests include Design Automation for VLSI, particulary physical design and timing optimization and combinatorial optimization. He has also interned at IBM Austin Research Laboratory in 2001, 2002 and 2003. He has also been awarded IBM graduate fellowship for the 2003-2004 academic year.Team Member: Devangkumar Jariwala Advisor: John Lillis University: University of Illinois at Chicago Devangkumar Jariwala received his B.E. degree in Electrical Engineering from Regional Engineering College, Surat, India. Currently, he is pursuing Ph.D. in Computer Science Department at University of Illinois at Chicago. His areas of interest include combinatorial optimization and CAD for VLSI, particularly physical design. He interned at Intel Corporation in Summer 2003.Official Team Number: 6 Team: SteamTeam Member: Paul T. DargaAdvisor: Karem A. Sakallah University: University of Michigan Paul is a Ph.D. pre-candidate in Computer Science and Engineering at the University of Michigan, under the supervision of Karem Sakallah. He received his B.S. in Computer Science and Mathematics at the University of Detroit Mercy in 2001, and will receive his M.S. in Computer Science and Engineering from the University of Michigan in December. His research has focused on exploiting structure in Boolean satisfiability.Team Member: Zaher S. Andraus Advisor: Karem A. Sakallah University: University of Michigan Zaher got his B.S.C. in Computer Engineering from the Israel Institute of Technology (Technion) in 2002. He is currently a Ph.D. student in Computer Science at the University of Michigan under the supervision of Karem Sakallah, with research focused on verification. Besides the CAD development at the University of Michigan, Zaher developed CAD tools during his part-time job at Intel (2000-2002), his summer internship at Synopsys (2003), and his undergraduate projects at the Technion.Official Team Number: 7 Team: LonghornsTeam Member: Kedarnath BalakrishnanAdvisor: Nur Touba University: University of Texas at Austin Balakrishnan is a doctoral candidate in Computer Engineering at the University of Texas at Austin. He earned a Bachelor's degree in Electrical Engineering from the Indian Institute of Technology, Bombay in 2000. His research interests include VLSI testing and and design for test.Team Member: Amit Prakash Advisor: Adnan Aziz University: University of Texas at Austin Amit Prakash is a 5th yr. graduate student at the University of Texas at Austin. After earning his bachelor's degree in electrical engineering degree from the Indian Institute of Technology, Kanpur, he spent a year at Synopsys working in hardware-software co-verification. His research interests include architectures and algorithms for high speed networking. He has also worked on logic synthesis techniques for packet classification.Official Team Number: 17 Team: EurekaTeam Member: Karthik KrishnamoorthyAdvisor: Florin Balasa University: University of Illinois at Chicago He received his B.E. degree in Electronics Engineering from the University of Bombay, Bombay, India. Currently, he is pursuing a Ph.D degree in Electrical and Computer Engineering at the University of Illinois at Chicago. Areas of interest include CAD for VLSI, especially analog floorplanning/placement and routing, high level synthesisTeam Member: Sarat Chandra Maruvada Advisor: Florin Balasa University: University of Illinois at Chicago He is a second year graduate student in the CS department at the University of Illinois at Chicago. He received his Masters in Computer Science in 2002 from the University of Illinois. His research interests include Analog IC design and VLSI CAD.Official Team Number: 13 Team: LeoTeam Member: Yiping FanAdvisor: Jason Cong University: UCLA He is a Ph.D. student in VLSI CAD Lab, Computer Science Department, UCLA.Team Member: Guoling Han Advisor: Jason Cong University: UCLA He is a Ph.D. student in VLSI CAD Lab, Computer Science Department, UCLA.Official Team Number: 8 Team: UCB16Team Member: Satrajit ChatterjeeAdvisor: Robert Brayton University: University of California, Berkeley Satrajit is a third year graduate student in the EECS department at University of California, Berkeley. He received his Bachelors and Masters in Electrical Engineering from the Indian Institute of Technology, Mumbai. His current research interests include placement driven synthesis for VLSI circuits and formal methods for equivalence checking.Team Member: Kaushik Ravindran Advisor: Kurt Keutzer University: University of California, Berkeley Kaushik is a third year graduate student in the EECS department at University of California, Berkeley. He received his Bachelors in Computer Engineering from Georgia Institute of Technology, Atlanta. His research interests include system level design for modern embedded systems and methods for statistical timing analysis.Official Team Number: 16 |
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