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SIGDA's CADathlon at ICCAD

Sunday, Nov. 7, 2004
8 am - 6 pm
Double Tree Hotel
San Jose, CA



 

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CADathlon 2003



  Sponsored by SIGDA
 
SIGDA Contact
Dr. Soha Hassoun

Problem Hints and References


To download the tar.gz file for all related papers, click here.

Problem 1: Analysis & Circuit Design

Overview: This problem concerns the computation of the path delay of interconnect structures in a simplified setting.
"Asymptotic Waveform Evaluation for Timing Analysis", Lawrence T. Pillage, Ronald A. Rohrer, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 4, April 1990

Problem 2: Physical Design

Overview: The problem concerns programming a method to construct a clock tree that is tolerant to changes in the width of interconnect wires.
"Process variation aware clock tree scheduling", Bing Lu, Jiang Hu, Gary Ellis, and Haihua Su, Proceedings of the 2003 International Symposium on Physical Design, 2003, pp. 174-181

Problem 3: Logic & High-Level Synthesis

Overview: Find a delay-optimal mapping of a combinational circuit using a particular library.
"DAGON: Technology Binding and Local Optimization in DAG Matching", Kurt Keutzer, Proceedings 24th Design Automation Conference, 1987, pp. 341-347

Problem 4: System Design and Analysis

Overview: This paper describes a few heuristics that are used for register allocation in compilers. Although the paper seems lengthy, it is not. Section 2 is what you want to focus on.
"Coloring Heuristics for Register Allocation", Preston Briggs, Keith D. Cooper, Ken Kennedy, and Linda Torcson, Proceedings of the ACM SIGPLAN '89 Conference on Programming Language Design and Implementation, July 1989, pp. 275-284

Problem 5: Functional Verification

Overview: The programming task concerns using transitive closure in satisfiability problems.
"A Transitive Closure based Algorithm for Test Generation", Srimat T. Chakradhar, Vishwani D. Agrawal, Proceedings of the 28th Design Automation Conference, 1991, pp. 353-358

Problem 6: Timing, Test, and Manufacturing

Overview: This problem focuses on issues in test vector compression for digital circuits.
"An Efficient Test Vector Compression Scheme Using Selective Huffman Coding", Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, and Nur A. Touba, IEEE Transactions on Computer-Aided Design, Vol. 22, No. 6, June 2003, pp. 797-805

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