Publications & Patents for Soha Hassoun

Soha Hassoun, "Genetic/Bio Design Automation for (Re-)engineering Biological Systems", Design and Test in Europe, 2012.

Nauman Khan, and Soha Hassoun, "The Feasibility of Carbon Nanotubes for Power Delivery in 3-D Integrated Circuits", Asia-Pacific Design Automation Conference (ASP-DAC), January, 2012.

Gautham Sridharan, Soha Hassoun, and Kyongbum Lee, "Identification of Biochemical Network Modules based on Shortest Retroactive Distances", PLoS Computational Biology, 2011.

Nauman Khan, Syed Alam, and Soha Hassoun, "Power Delivery Design For 3-D ICs Using Different Through-Silicon Via (TSV) Technologies", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 647 - 658, March, 2011

Mona Yousofshahi, Kyongbum Lee, and Soha Hassoun, "Probabilistic Pathway Construction", Metabolic Engineering, 13 (2011) 435-444.

Nauman Khan, Syed Alam, and Soha Hassoun, "Mitigating TSV-induced Substrate Noise in 3-D ICs using GND Plugs", International Symposium on Quality Electronic Design (ISQED), 2011

Jinhai Qiu, Sherief Reda, and Soha Hassoun, "Fast, Accurate Routing Delay Estimation", International Workshop on System Level Interconnect Prediction (SLIP), pp. 77 - 82, 2010.

Nauman Khan, Sherief Reda, and Soha Hassoun, "Early Estimation Of TSV Area For Power Delivery In 3-D Integrated Circuits", IEEE International Conference on 3D System Integration (3DIC), 2010, 1-6

John Rieffel, Frank Saunders, Shilpa Nadimpalli, Harvey Zhou, Soha Hassoun, Jason Rife, Barry Trimmer, "Evolving Soft Robotic Locomotion In Physx", GECCO '09 Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference

Nauman Khan, Syed Alam, and Soha Hassoun, "System-Level Comparison Of Power Delivery Design For 2D And 3D ICs", IEEE International Conference on 3D System Integration (3DIC), 2009

Nauman Khan, Syed Alam, and Soha Hassoun, "Through-Silicon Via (TSV)-Induced Noise Characterization And Noise Mitigation Using Coaxial TSVs", IEEE International Conference on 3D System Integration (3DIC), 2009

Ehsan Ullah, Kyongbum Lee, and Soha Hassoun, "An Algorithm For Identifying Dominant-Edge Metabolic Pathways", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 144 - 150, 2009

Brian Swahn and Soha Hassoun, "Electro-Thermal Analysis of Multi-Fin Devices", IEEE Transactions on Very Large Scale Integration (VLSI), 816-829, July 2008

Brian Swahn and Soha Hassoun, "Gate Sizing - Finfets Vs 32Nm Bulk Mosfets", IEEE/ACM Design Automation Conference, July, 2006

Brian Swahn and Soha Hassoun, "METS - A Metric For Electro-Thermal Sensitivity, And Its Application To Finfets", International Symposium on Quality Electronic Design (ISQED), 2006

Soha Hassoun, M. Kudlugi, C. Selvidge, and D. Pryor, "A Transaction-Based Unified Architecture for Simulation and Emulation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 2, February, 2005, p 278-287

Soha Hassoun and C. Alpert, "Optimal Path Routing in Single- and Multiple-Clock Domain Systems", IEEE Transaction on Computer-Aided Design, November, 2003

Soha Hassoun, C., Cromer, and E. Calvillo-Gamez, "Static Timing Analysis For Level-Clocked Circuits In The Presence Of Crosstalk", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v 22, n 9, p 1270-7, Sept. 2003

Brian Swahn and Soha Hassoun, "Hardware Scheduling for Dynamic Adaptability Using External Profiling and Hardware Threading", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 58-64, 2003

Soha Hassoun, "Optimal Use Of 2-Phase Transparent Latches In Buffered Maze Routing", International Symposium on Circuits and Systems (ISCAS), IV-688 - IV-691 vol.4

Soha Hassoun and Geert Janssen, "First CADathlon Programming Contest Held at 2002 ICCAD", IEEE Design and Test Magazine, pp. 104-107, May-June, 2003.

Soha Hassoun and Diana Marculescu, "Towards GALS Design Methodologies", Workshop on Formal Methods For Globally Asynchronous Locally Synchronous (GALS) Architecture, September, 2003

Fadi Aloul, Soha Hassoun, K. Sakallah, and D. Blaauw, "Robust SAT-Based Search Algorithm For Leakage Power Reduction", International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Soha Hassoun, C. Alpert, and M. Thiagarajan, "Optimal Buffered Routing Path Constructions For Single And Multiple Clock Domain Systems", IEEE/ACM International Conference on Computer Aided Design (ICCAD), p 247-53, 2002

Soha Hassoun, C., Cromer, and E. Calvillo-Gamez, "Verifying Clock Schedules in the Presence of Cross Talk", Design, Automation and Test in Europe Conference (DATE), 2002.

Soha Hassoun and T. Sasao, Editors, "Logic Synthesis and Verification", Kluwer Academic Publishers, 2002.

Soha Hassoun and T. Villa, "Optimization of Synchronous Circuits", a chapter in "Logic Synthesis and Verification", editors: Hassoun and Sasao, Kluwer Academic Publishers, pp. 225-253, 2002.

Soha Hassoun and Soheila Bana, "Practices For Recruiting And Retaining Graduate Women Students In Computer Science And Engineering", International Conference on Microelectronic Systems Education, 2001

Kudlugi, M.; Hassoun, S.; Selvidge, C.; Pryor, D., "A Transaction-Based Unified Simulation/Emulation Architecture For Functional Verification", IEEE/ACM Design Automation Conference (DAC), p 623-8, 2001

Soha Hassoun, "Critical Path Analysis Using A Dynamically Bounded Delay Model", IEEE/ACM Design Automation Conference (DAC), 260-265, June, 2000

Soha Hassoun, and C. McCreary, "Regularity Extraction Via Clan-Based Structural Circuit Decomposition", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 414-419, November, 1999

Soha Hassoun, "Fine Grain Incremental Rescheduling Via Architectural Retiming", International Symposium on System Synthesis (ISSS), pp. 158-163, December, 1998

Soha Hassoun and Carl Ebeling, "Using Precomputation In Architecture And Logic Resynthesis", International Conference on Computer-Aided Design (ICCAD), pp. 316-423, November, 1998

Soha Hassoun and Carl Ebeling, "An Overview Of Prediction-Based Architectural Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December, 1997

Soha Hassoun and Carl Ebeling, "Experiments In The Iterative Application Of Resynthesis And Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December, 1997

Soha Hassoun and Carl Ebeling, "Architectural Retiming - Pipelining Latency-Constrained Circuits", IEEE/ACM Design Automation Conference (DAC), 708-713, 1996

Soha Hassoun and Carl Ebeling, "Architectural Retiming - An Overview", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 1995

Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo,Robert Wille, "The Chaos Router Chip: Design and Implementation of an Adaptive Router", International Conference on Very Large Scale Integration (VLSI), p. 311-20, 1994

Soha Hassoun and Gaetano Borriello, "Improving Finite State Assignment for Two-Level Programmable Logic Devices", International Workshop on Logic Synthesis (IWLS), May, 1993

D. Dobberpuhl, R. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R. Conrad, D. Dever, B. Gieseke, Soha Hassoun, G. Hoeppner, K. Kuchler, M. Ladd, B. Leary, L. Madden, E. McLellan, D. Meyer, J. Montanaro, D. Priore, V. Rajagopalan, S. Samudrala, S. Santhanam. "A 200 MHz 64-b Dual-Issue CMOS Microprocessor, "A 200-Mhz 64-B Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, November, 1992, Vol. 27, No. 11. Also appears in Digital Technical Journal. Vol. 4, No. 4, 1992

R. Allmon, B. Benschneider, M. Callander, L. Chao, D. Dever, J. Farrell, N. Fitzgerald, J. Grodstein, Soha Hassoun, L. Hudepohl, D. Kravitz, J. Lundberg, R. Marcello, S. Marino, J. Pickholtz, R. Preston, M. Richesson, S. Samudrala, and D. Sanders, "System, Process, And Design Implications Of A Reduced Supply Voltage Microprocessor", IEEE International Solid-State Circuits Conference (ISSCC), February, 1990

W. Dally, L. Chao, A. Chien, Soha Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty, and S. Wills, "Architecture Of A Message-Driven Processor", International Symposium on Computer Architecture (ISCA), June, 1987. (A re-write of this article appears in the Best of ISCA 2000.)

N. Khan, S. Hassoun, an S. Alam, "Mitigating TSV-induced Substrate Noise in a 3-D Integrated Circuit", provisional filed in March 2011

S. Hassoun and B. Swahn, "Circuit Having Hardware Threading", US Patent 7,797,64740435

C. Selvidge, K. Crouch, M. Kudlugi, and S. Hassoun, "Non-synchronized multiplex data transport across synchronous systems", US Patent 6,961,69138657

C. Alpert and S. Hassoun , "Optimal Buffered Routing Path Constructions for Single and Multiple Clock Domain Systems", US Patent 6,915,36138538

S. Hassoun and D. Sanders, "Method and Apparatus for Parity Generation", US Patent 5,557,62235325