This simulation models a single critical path. We start with CLK, the root of the clock tree (e.g., a PLL output). You can control its clock period with the "clock-period" slider.
CLK drives one common buffer used for both the driver- and receiver-flop clocks, (marked "com"). The clock tree then splits; one buffer (marked "dr") drives the clock for the first flop on the critical path, and a second buffer (marked "rx") drives the clock for the second flop (the one that receives the data).
Each of the three clock buffers just described has skew and jitter, which with can control with 3 sliders. The "Jitter in cycle 1" and "Jitter in cycle 2" set the jitter amount for the first and second clock rising edges respectively. The "skew" slider sets skew, which is identical in all cycles.
By setting the sliders for the common and driver buffers, you can control when the rising edge of CLK_dr occurs. This then launches the critical path. It drives a flop, which drives a logic block. All of these delays are shown in the plot (yellow for the common buffer, light blut for the driver buffer, and orange for the logic block). The path ends at the output of the logic block.
If the logic block settles later than the second edge of the Rx clock, then it is a timing violation (shown in red); otherwise we have timing margin (shown in green). You can play with the sliders to make the critical path pass or fail.