This small web app computes gate delay. The top form specifies technology constants. You can use the ones given (which are the ones we used in class), or change them if you like. For example, you could change them to model the effect of process variations on delay.
The bottom form specifies the parameters of a single gate driving a wire and a downstream load.
The driving device is assumed to be an inverter; you specify the W,L of the N device. You could just give the Neff of, e.g., a NAND gate -- but the self-loading cap would then be underestimated.
For ease of use, you can specify the downstream load in femptofarads (i.e., a fixed capacitor) and/or in DU^2 (i.e., a gate cap); if you specify both, then they get added together. If you use DU^2, note that you must specify the total of both N and P devices.
The resulting delay gets calculated and displayed below the two forms. We also display the total resistance and capacitance (which should satisfy Rtotal*Ctotal=Delay).