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Thermal Analysis of Multi-Fin Devices
Authors: Swahn, Brian; Hassoun, Soha
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As device dimensions shrink into the nanometer range, power and performance constraints prohibit the longevity of traditional MOS devices in circuit design. FinFETs, a quasi-planar double-gated device, has emerged as a replacement. FinFETs are formed by creating a silicon "fin" which protrudes out of the wafer, wrapping a gate around the fin, and then doping the ends of the fin to form the source and drain regions. Wider finFETs are formed using multiple fins between the source and drain regions.

While finFETs provide promising electrostatic characteristics, they, like other ultra-thin body nano devices, have the potential to suffer from significant self heating. We study in this paper self heating in multi-fin devices. We first propose a flared channel extension thermal model of each individual fin. We then extend the model to accommodate for multi-fin devices. We analyze several fin geometric parameters (fin width, and (gate) length) and investigate how fin spacing, fin height, gate oxide thickness and gate height affect the maximum fin temperatures in rectangular and flared channel extensions. We provide experimental data to validate our findings. We conclude with developing a novel metric, METS (Metric for Electro-Thermal Sensitivity), for measuring device thermal robustness using electro-thermal simulations and use the metric to investigate device sensitivities in different regions of operation.

Our work is novel as it is the first to address thermal issues within multi-fin devices and develop a metric, METS, for evaluating device sensitivities in different regions of operation. The metric, while applied to finFETs, is general and can be applied to any type of device for which coupled electrical and thermal models exist. Furthermore, this work provides an impetus for further research on the emerging area of electro-thermal device and circuit design.

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