Soha Hassoun
Associate Professor and Chair
Department of Computer Science

Adjunct Associate Professor
Department of Electrical and Computer Engineering
Department of Chemical and Biological Engineering

School of Engineering
Tufts University


center> CV
Publications & Patents
Service
Teaching
Students

contact info
+1 617 627 5177 | Skype Me<!--
! | soha @ cs.tufts.edu | View Soha Hassoun's LinkedIn profile
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US Postal: 161 College Ave, Medford, MA 02155, USA

Publications

G. Sridharan, E. Ullah, S. Hassoun, and K. Lee, "Discovery of Substrate Cycles in Large Scale Metabolic Networks Using Hierarchical Modularity", accepted for publication, BMC Systems Biology

Brad Gaynor and Soha Hassoun, "Simulation Methodology and Evaluation of Through-Silicon Via (TSV)-FinFET Noise Coupling in 3-D Integrated Circuit", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume:PP, Issue: 99, August, 2014

Brad Gaynor and Soha Hassoun, "Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design", IEEE Transactions on Electron Devices 2014, PP:99 doi:10.1109/TED.2014.2331190

Mona Yousofshahi, Ehsan Ullah, Russell Stern and Soha Hassoun, "MC3: A Steady-State Model and Constraint Consistency Checker for Biochemical Networks", BMC Systems Biology 2013, 7:129 doi:10.1186/1752-0509-7-129

Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, and Soha Hassoun "Probabilistic strain optimization under constraint uncertainty", BMC Systems Biology 2013, 7:29 doi:10.1186/1752-0509-7-29

Brad Gaynor and Soha Hassoun, "Parasitic Back-Gate Effect in 3-D Fully Depleted Silicon on Insulator Integrated Circuits", IEEE Transactions on Components, Packaging and Manufacturing Technology, Issue 99, 2013

Nauman Khan, Syed Alam, and Soha Hassoun, "GND Plugs: A Superior Technology to Mitigate TSV-Induced Substrate Noise", IEEE Transactions on Components, Packaging and Manufacturing Technology, March 26, 2013

Gautham Vivek Sridharan, Michael Yi, Soha Hassoun and Kyongbum Lee, "Metabolic Flux-Based Modularity using Shortest Retroactive Distances", BMC Systems Biology, 2012, 6:155 http://www.biomedcentral.com/1752-0509/6/155

Doug Densmore and Soha Hassoun, "Design Automation for Synthetic Biological Systems", IEEE Design & Test of Computers, Volume:29 , Issue: 3, May/June 2012.

Soha Hassoun, "Genetic/Bio Design Automation for (Re-)engineering Biological Systems", Design and Test in Europe, 2012.

Nauman Khan, and Soha Hassoun, "The Feasibility of Carbon Nanotubes for Power Delivery in 3-D Integrated Circuits", Asia-Pacific Design Automation Conference (ASP-DAC), January, 2012.

Gautham Sridharan, Soha Hassoun, and Kyongbum Lee, "Identification of Biochemical Network Modules based on Shortest Retroactive Distances", PLoS Computational Biology, 2011.

Nauman Khan, Syed Alam, and Soha Hassoun, "Power Delivery Design For 3-D ICs Using Different Through-Silicon Via (TSV) Technologies", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 4, pp. 647 - 658, March, 2011

Mona Yousofshahi, Kyongbum Lee, and Soha Hassoun, "Probabilistic Pathway Construction", Metabolic Engineering, 13 (2011) 435-444.

Nauman Khan, Syed Alam, and Soha Hassoun, "Mitigating TSV-induced Substrate Noise in 3-D ICs using GND Plugs", International Symposium on Quality Electronic Design (ISQED), 2011

Jinhai Qiu, Sherief Reda, and Soha Hassoun, "Fast, Accurate Routing Delay Estimation", International Workshop on System Level Interconnect Prediction (SLIP), pp. 77 - 82, 2010.

Nauman Khan, Sherief Reda, and Soha Hassoun, "Early Estimation Of TSV Area For Power Delivery In 3-D Integrated Circuits", IEEE International Conference on 3D System Integration (3DIC), 2010, 1-6

John Rieffel, Frank Saunders, Shilpa Nadimpalli, Harvey Zhou, Soha Hassoun, Jason Rife, Barry Trimmer, "Evolving Soft Robotic Locomotion In Physx", GECCO '09 Proceedings of the 11th Annual Conference Companion on Genetic and Evolutionary Computation Conference

Nauman Khan, Syed Alam, and Soha Hassoun, "System-Level Comparison Of Power Delivery Design For 2D And 3D ICs", IEEE International Conference on 3D System Integration (3DIC), 2009

Nauman Khan, Syed Alam, and Soha Hassoun, "Through-Silicon Via (TSV)-Induced Noise Characterization And Noise Mitigation Using Coaxial TSVs", IEEE International Conference on 3D System Integration (3DIC), 2009

Ehsan Ullah, Kyongbum Lee, and Soha Hassoun, "An Algorithm For Identifying Dominant-Edge Metabolic Pathways", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 144 - 150, 2009

Brian Swahn and Soha Hassoun, "Electro-Thermal Analysis of Multi-Fin Devices", IEEE Transactions on Very Large Scale Integration (VLSI), 816-829, July 2008

Brian Swahn and Soha Hassoun, "Gate Sizing - Finfets Vs 32Nm Bulk Mosfets", IEEE/ACM Design Automation Conference, July, 2006

Brian Swahn and Soha Hassoun, "METS - A Metric For Electro-Thermal Sensitivity, And Its Application To Finfets", International Symposium on Quality Electronic Design (ISQED), 2006

Soha Hassoun, M. Kudlugi, C. Selvidge, and D. Pryor, "A Transaction-Based Unified Architecture for Simulation and Emulation", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 2, February, 2005, p 278-287

Soha Hassoun and C. Alpert, "Optimal Path Routing in Single- and Multiple-Clock Domain Systems", IEEE Transaction on Computer-Aided Design, November, 2003

Soha Hassoun, C., Cromer, and E. Calvillo-Gamez, "Static Timing Analysis For Level-Clocked Circuits In The Presence Of Crosstalk", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v 22, n 9, p 1270-7, Sept. 2003

Brian Swahn and Soha Hassoun, "Hardware Scheduling for Dynamic Adaptability Using External Profiling and Hardware Threading", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 58-64, 2003

Soha Hassoun, "Optimal Use Of 2-Phase Transparent Latches In Buffered Maze Routing", International Symposium on Circuits and Systems (ISCAS), IV-688 - IV-691 vol.4

Soha Hassoun and Geert Janssen, "First CADathlon Programming Contest Held at 2002 ICCAD", IEEE Design and Test Magazine, pp. 104-107, May-June, 2003.

Soha Hassoun and Diana Marculescu, "Towards GALS Design Methodologies", Workshop on Formal Methods For Globally Asynchronous Locally Synchronous (GALS) Architecture, September, 2003

Fadi Aloul, Soha Hassoun, K. Sakallah, and D. Blaauw, "Robust SAT-Based Search Algorithm For Leakage Power Reduction", International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), 2002.

Soha Hassoun, C. Alpert, and M. Thiagarajan, "Optimal Buffered Routing Path Constructions For Single And Multiple Clock Domain Systems", IEEE/ACM International Conference on Computer Aided Design (ICCAD), p 247-53, 2002

Soha Hassoun, C., Cromer, and E. Calvillo-Gamez, "Verifying Clock Schedules in the Presence of Cross Talk", Design, Automation and Test in Europe Conference (DATE), 2002.

Soha Hassoun and T. Sasao, Editors, "Logic Synthesis and Verification", Kluwer Academic Publishers, 2002.

Soha Hassoun and T. Villa, "Optimization of Synchronous Circuits", a chapter in "Logic Synthesis and Verification", editors: Hassoun and Sasao, Kluwer Academic Publishers, pp. 225-253, 2002.

Soha Hassoun and Soheila Bana, "Practices For Recruiting And Retaining Graduate Women Students In Computer Science And Engineering", International Conference on Microelectronic Systems Education, 2001

Kudlugi, M.; Hassoun, S.; Selvidge, C.; Pryor, D., "A Transaction-Based Unified Simulation/Emulation Architecture For Functional Verification", IEEE/ACM Design Automation Conference (DAC), p 623-8, 2001

Soha Hassoun, "Critical Path Analysis Using A Dynamically Bounded Delay Model", IEEE/ACM Design Automation Conference (DAC), 260-265, June, 2000

Soha Hassoun, and C. McCreary, "Regularity Extraction Via Clan-Based Structural Circuit Decomposition", IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 414-419, November, 1999

Soha Hassoun, "Fine Grain Incremental Rescheduling Via Architectural Retiming", International Symposium on System Synthesis (ISSS), pp. 158-163, December, 1998

Soha Hassoun and Carl Ebeling, "Using Precomputation In Architecture And Logic Resynthesis", International Conference on Computer-Aided Design (ICCAD), pp. 316-423, November, 1998

Soha Hassoun and Carl Ebeling, "An Overview Of Prediction-Based Architectural Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December, 1997

Soha Hassoun and Carl Ebeling, "Experiments In The Iterative Application Of Resynthesis And Retiming", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), December, 1997

Soha Hassoun and Carl Ebeling, "Architectural Retiming - Pipelining Latency-Constrained Circuits", IEEE/ACM Design Automation Conference (DAC), 708-713, 1996

Soha Hassoun and Carl Ebeling, "Architectural Retiming - An Overview", International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 1995

Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo,Robert Wille, "The Chaos Router Chip: Design and Implementation of an Adaptive Router", International Conference on Very Large Scale Integration (VLSI), p. 311-20, 1994

Soha Hassoun and Gaetano Borriello, "Improving Finite State Assignment for Two-Level Programmable Logic Devices", International Workshop on Logic Synthesis (IWLS), May, 1993

D. Dobberpuhl, R. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R. Conrad, D. Dever, B. Gieseke, Soha Hassoun, G. Hoeppner, K. Kuchler, M. Ladd, B. Leary, L. Madden, E. McLellan, D. Meyer, J. Montanaro, D. Priore, V. Rajagopalan, S. Samudrala, S. Santhanam. "A 200 MHz 64-b Dual-Issue CMOS Microprocessor, "A 200-Mhz 64-B Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, November, 1992, Vol. 27, No. 11. Also appears in Digital Technical Journal. Vol. 4, No. 4, 1992

R. Allmon, B. Benschneider, M. Callander, L. Chao, D. Dever, J. Farrell, N. Fitzgerald, J. Grodstein, Soha Hassoun, L. Hudepohl, D. Kravitz, J. Lundberg, R. Marcello, S. Marino, J. Pickholtz, R. Preston, M. Richesson, S. Samudrala, and D. Sanders, "System, Process, And Design Implications Of A Reduced Supply Voltage Microprocessor", IEEE International Solid-State Circuits Conference (ISSCC), February, 1990

W. Dally, L. Chao, A. Chien, Soha Hassoun, W. Horwat, J. Kaplan, P. Song, B. Totty, and S. Wills, "Architecture Of A Message-Driven Processor", International Symposium on Computer Architecture (ISCA), June, 1987. (A re-write of this article appears in the Best of ISCA 2000.)


Patents

B. Gaynor and S. Hassoun, "Integrated Circuit with Multi-Threshold Bulk FinFETst", provisional filed in March 2014

N. Khan, S. Hassoun, and S. Alam, "Mitigating TSV-induced Substrate Noise in a 3-D Integrated Circuit", US2012/029003

S. Hassoun and B. Swahn, "Circuit Having Hardware Threading", US Patent 7,797,64740435

C. Selvidge, K. Crouch, M. Kudlugi, and S. Hassoun, "Non-synchronized multiplex data transport across synchronous systems", US Patent 6,961,69138657

C. Alpert and S. Hassoun , "Optimal Buffered Routing Path Constructions for Single and Multiple Clock Domain Systems", US Patent 6,915,36138538

S. Hassoun and D. Sanders, "Method and Apparatus for Parity Generation", US Patent 5,557,62235325


Service

Professional Executive Leadership Roles

  • Chair, Design Automation Conference (DAC), the premier conference in Design Automation with an annual budget of over $2.5M and over 100 volunteers, 2014
  • Vice Chair, Design Automation Conference (DAC), 2013
  • Member, Executive Committee, Design Automation Conference (DAC), 2011-2014
  • General Chair, International Conference on Computer-Aided Design (ICCAD), 2006
  • Vice Chair, the International Conference on Computer-Aided Design (ICCAD), 2005
  • Member, Executive Committee, the International Conference on Computer-Aided Design (ICCAD), 2001-2007
  • Chair, The International Workshop on Logic and Synthesis, 2002
  • Co-Founder, the International Workshop on Biology Design Automation (IWBDA), 2009
  • Steering committee member, the International Workshop on Biology Design Automation (IWBDA), 2009-2012

Professional Technical Leadership Roles

  • Technical Program Co-Chair, Design Automation Conference (DAC), 2012-2011
  • Design Community Chair, Design Automation Conference (DAC), 2010-2009
  • Technical Program Chair, the International Conference on Computer-Aided Design (ICCAD), the second largest conference in EDA at the time, 2004
  • Technical Program Co-Chair, the International Conference on Computer-Aided Design (ICCAD), 2003
  • Subcommittee Chair on Synthesis, Design Automation Conference (DAC), 2003-2005
  • Technical Program Chair, The International Workshop on Logic and Synthesis, 2001
  • Publicity Chair, the International Workshop on Bio Design Automation (IWBDA), 2010

Program Committees

  • ACM Conference on Bioinformatics, Computational Biology and Biomedical Informatics (ACM BCB), 2013
  • The International Conference on Computer-Aided Design (ICCAD), 2011-2013
  • Design Automation Conference (DAC), 2002-2005
  • The International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU), 2002-2006
  • The International Workshop on Biology Design Automation, 2009-present
  • The International Workshop on Logic and Synthesis (IWLS), 2001-2005

Editorship Roles

  • Associate Editor, IEEE Design and Test Magazine (D&T), 2002- 2011, 2013-present
  • Member, selection committee for the EIC for the ACM Transactions on Design Automation of Electronic Systems (TODAES), Fall 2013
  • Associate Editor, IEEE Transactions on Computer-Aided Design (TCAD), January 2002- January 2006

Guest Editorials

  • Guest Editor, with Yervant Zorian (Synopsys), for IEEE Design and Test Magazine special section on the 50th Design Automation Conference, May-June 2014
  • Guest Editor, with Douglas Densmore (Boston University), for IEEE Design and Test Magazine special section on Bio Design Automation, May-June 2012
  • Guest Editor, with Leon Stok (IBM Watson) and Steve Nowick (Columbia), for IEEE Transactions on Computer-Aided Design special issue on Logic Synthesis, May 2003
  • Guest Editor, with Sani Nassif (IBM Austin Research Labs) for IEEE Design and Test Magazine special issue on Power Grid Design and Analysis, May-June 2003
  • Guest Editor, with Yong-Bin Kim (Northeastern) and Fabrizio Lombardi (Northeastern), for IEEE Design and Test Magazine special issue on Clockless Design, November-December 2003

Professional Society Leadership Roles

  • Vice President of Technical Activities, IEEE CEDA (Council on Design Automation), 2007-2008
  • Advisory Board member, ACM's Special Interest on Design Automation (SIGDA), 1999-2004
  • Director of Educational Activities, ACM/SIGDA, 2001-2004
  • Member, the CACM (Communication of the ACM) Task Force, A group of dynamic individuals charged by then President of ACM, David Patterson, to remap the key flag publication, 2004

Reviewing and Best Paper Selection Committees

  • Reviewer, IEEE Transactions on Computer-Aided Design, ACM Transaction on Design Automation of Electronic Systems, IEEE Transaction on VLSI, IEEE Transaction on Electron Devices, IEEE Transactions on Components, Packaging and Manufacturing Technology, ACM Journal on Emerging Technologies in Computing Systems, IEEE Transactions on Electron Devices, Bioinformatics, PLOS ONE
  • Panelist, NSF Panels in 2014, 2012, 2011, 2010, 2009, 2008, 2007, 2004, 2003, 2002; MICRO program, 2004, 2003; NIH 2012
  • Member, Best paper selection committee, ICCAD 2003
  • Member, Best paper selection committee, DAC 2010
  • Chair, Best paper committee, DAC 2011

Diversity/Outreach Service

  • Member , Grace Hopper Celebration for Women Scholarship Application Committee, 2014
  • Co-organizer, CRAW/CDC Discipline Specific Workshop on Diversity in Design Automation, San Francisco, May 2014, with funding from CRA-W, NSF, ACM/SIGDA, and IEEE CEDA
  • Co-organizer, 2012 Young Faculty Workshop at DAC, San Francisco, June 2012

Other Service

  • Founded, organized, and oversaw for several years the following programs: The Ph. D. Forum at DAC (founded: 1997, Overseer: 1997-2002), the CADathlon Programming Contest at ICCAD (International Conference on Computer-Aided Design) (founded 2003, Overseer 2003-2007), and the Design Automation Summer School (founded 2001, Overseer in 2001, 2005, 2007)
  • Member, Defense Science Study Group, Institute for Defense Analysis, Nominated by Tufts Dean of Engineering and appointed by DARPA, 2009-2011

Society Memberships

  • IEEE, senior member
  • ACM, member
  • AIChE, member
  • Society of Biological Engineers, member

Tufts Departmental Service

  • Chair, Department of Computer Science, 09/2013-present
  • Co-Founder and Contact Person, Tufts Young CS Alum group, 08/2013-present
  • Associate Chair, Department of Computer Science, 09/2012-05/2013
  • Member, search committee for Bridge Professorship in Cognitive Science, 02/2014-present
  • Graduate Program Director, 2005-2006, and member of the graduate committee 2001-2007
  • Faculty search committee, 2003-2004, 2004-2005, 2008-2009
  • Undergraduate Committee Chair, 2008-2009
  • Organizer, CS department seminars, Fall 2013; EECS department seminars, Fall 2000, Spring 2001, Fall 2001
  • Member, Computer Engineering Curriculum Committee, EECS department, 1999-2001

Tufts University Service

  • Chair, Research Day on Data Science, May 2014
  • Member, Council on Diversity at Tufts, 09/2012-12/2013
  • Fellow, Tisch College of Citizenship and Public Service, 2010-2011
  • Member, Faculty Research Award Committee, 09/2009-05/2013
  • Fellow, Tufts Center for the Enhancement of Learning and Teaching (CELT), 2009-2010
  • Member, Campus Planning and Development Committee (CPDC), 09/2001- 05/2005
  • Member, Equal Educational Opportunity Committee (EEOC), 09/2001- 05/2004
  • Attendee, Critical Thinking Faculty Workshop at Tufts, May, 5/1999
  • Attendee, Faculty Workshop on Teaching Diverse Student Populations, 5/1998